| Message ID | 20220929222647.23816-1-hal.feng@linux.starfivetech.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Basic StarFive JH7110 RISC-V SoC support | expand |
On Fri, 30 Sep 2022 06:26:47 +0800, Hal Feng wrote: > From: Emil Renner Berthing <kernel@esmil.dk> > > Add bindings for the system clock generator on the JH7110 > RISC-V SoC by StarFive Technology Ltd. > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com> > --- > .../clock/starfive,jh7110-clkgen-sys.yaml | 69 +++++++++++++++++++ > 1 file changed, 69 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.example.dts:18.47-31.11: Warning (unit_address_vs_reg): /example-0/clock-controller@13020000: node has a unit name, but no reg or ranges property doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On 30/09/2022 00:26, Hal Feng wrote: > From: Emil Renner Berthing <kernel@esmil.dk> > > Add bindings for the system clock generator on the JH7110 > RISC-V SoC by StarFive Technology Ltd. > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com> (...) > + '#clock-cells': > + const: 1 > + description: > + See <dt-bindings/clock/starfive-jh7110-sys.h> for valid indices. > + > +required: > + - compatible > + - clocks > + - clock-names > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + syscrg_clk: clock-controller@13020000 { Does not look like you tested the bindings. Please run `make dt_binding_check` (see Documentation/devicetree/bindings/writing-schema.rst for instructions). > + compatible = "starfive,jh7110-clkgen-sys"; > + clocks = <&osc>, <&gmac1_rmii_refin>, > + <&gmac1_rgmii_rxin>, > + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, > + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, > + <&tdm_ext>, <&mclk_ext>; > + clock-names = "osc", "gmac1_rmii_refin", > + "gmac1_rgmii_rxin", > + "i2stx_bclk_ext", "i2stx_lrck_ext", > + "i2srx_bclk_ext", "i2srx_lrck_ext", > + "tdm_ext", "mclk_ext"; > + #clock-cells = <1>; > + }; Best regards, Krzysztof
On Fri, 30 Sep 2022 12:58:12 +0200, Krzysztof Kozlowski wrote: > On 30/09/2022 00:26, Hal Feng wrote: > > From: Emil Renner Berthing <kernel@esmil.dk> > > > > Add bindings for the system clock generator on the JH7110 > > RISC-V SoC by StarFive Technology Ltd. > > > > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> > > Signed-off-by: Hal Feng <hal.feng@linux.starfivetech.com> > > (...) > > > + '#clock-cells': > > + const: 1 > > + description: > > + See <dt-bindings/clock/starfive-jh7110-sys.h> for valid indices. > > + > > +required: > > + - compatible > > + - clocks > > + - clock-names > > + - '#clock-cells' > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + syscrg_clk: clock-controller@13020000 { > > Does not look like you tested the bindings. Please run `make > dt_binding_check` (see > Documentation/devicetree/bindings/writing-schema.rst for instructions). Will rewrite the bindings and test them. Thanks. Best regards, Hal
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml new file mode 100644 index 000000000000..290b730145ab --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen-sys.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-clkgen-sys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 System Clock Generator + +maintainers: + - Emil Renner Berthing <kernel@esmil.dk> + - Xingyu Wu <xingyu.wu@linux.starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-clkgen-sys + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: RMII reference clock + - description: RGMII RX clock + - description: I2S TX bit clock + - description: I2S TX left/right clock + - description: I2S RX bit clock + - description: I2S RX left/right clock + - description: TDM + - description: mclk + + clock-names: + items: + - const: osc + - const: gmac1_rmii_refin + - const: gmac1_rgmii_rxin + - const: i2stx_bclk_ext + - const: i2stx_lrck_ext + - const: i2srx_bclk_ext + - const: i2srx_lrck_ext + - const: tdm_ext + - const: mclk_ext + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive-jh7110-sys.h> for valid indices. + +required: + - compatible + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + syscrg_clk: clock-controller@13020000 { + compatible = "starfive,jh7110-clkgen-sys"; + clocks = <&osc>, <&gmac1_rmii_refin>, + <&gmac1_rgmii_rxin>, + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, + <&tdm_ext>, <&mclk_ext>; + clock-names = "osc", "gmac1_rmii_refin", + "gmac1_rgmii_rxin", + "i2stx_bclk_ext", "i2stx_lrck_ext", + "i2srx_bclk_ext", "i2srx_lrck_ext", + "tdm_ext", "mclk_ext"; + #clock-cells = <1>; + };