Message ID | 20211229101530.22783-5-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
---|---|
State | Accepted |
Delegated to: | Pavel Machek |
Headers | show |
Series | Add sound/adc support for RZ/G2L | expand |
Hi! > From: Biju Das <biju.das.jz@bp.renesas.com> > > commit bed0b1c1e88a27b76c74584128cadebc6fa58622 upstream. > > The DMAC on RZ/G2L has specific slave channel configuration > parameters for SSI. > This patch updates the dmas description and example node to include > the encoded slave channel configuration. > +++ b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml > @@ -48,6 +48,24 @@ properties: > dmas: > minItems: 1 > maxItems: 2 > + description: > + The first cell represents a phandle to dmac > + The second cell specifies the encoded MID/RID values of the SSI port > + connected to the DMA client and the slave channel configuration > + parameters. > + bits[0:9] - Specifies MID/RID value of a SSI channel as below > + MID/RID value of SSI rx0 = 0x256 > + MID/RID value of SSI tx0 = 0x255 > + MID/RID value of SSI rx1 = 0x25a > + MID/RID value of SSI tx1 = 0x259 > + MID/RID value of SSI rt2 = 0x25f > + MID/RID value of SSI rx3 = 0x262 > + MID/RID value of SSI tx3 = 0x261 > + bit[10] - HIEN = 1, Detects a request in response to the rising edge > + of the signal > + bit[11] - LVL = 0, Detects based on the edge > + bits[12:14] - AM = 2, Bus cycle mode > + bit[15] - TM = 0, Single transfer mode I wish there was better solution to this. Device tree sources are quite human-readable, this really is not. Best regards, Pavel
Hi Pavel, Thank you for the review. > -----Original Message----- > From: Pavel Machek <pavel@denx.de> > Sent: 30 December 2021 10:55 > To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> > Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek > <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com> > Subject: Re: [PATCH 5.10.y-cip 04/31] ASoC: dt-bindings: renesas,rz-ssi: Update slave dma channel > configuration parameter > > Hi! > > > From: Biju Das <biju.das.jz@bp.renesas.com> > > > > commit bed0b1c1e88a27b76c74584128cadebc6fa58622 upstream. > > > > The DMAC on RZ/G2L has specific slave channel configuration parameters > > for SSI. > > This patch updates the dmas description and example node to include > > the encoded slave channel configuration. > > > +++ b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml > > @@ -48,6 +48,24 @@ properties: > > dmas: > > minItems: 1 > > maxItems: 2 > > + description: > > + The first cell represents a phandle to dmac > > + The second cell specifies the encoded MID/RID values of the SSI port > > + connected to the DMA client and the slave channel configuration > > + parameters. > > + bits[0:9] - Specifies MID/RID value of a SSI channel as below > > + MID/RID value of SSI rx0 = 0x256 > > + MID/RID value of SSI tx0 = 0x255 > > + MID/RID value of SSI rx1 = 0x25a > > + MID/RID value of SSI tx1 = 0x259 > > + MID/RID value of SSI rt2 = 0x25f > > + MID/RID value of SSI rx3 = 0x262 > > + MID/RID value of SSI tx3 = 0x261 > > + bit[10] - HIEN = 1, Detects a request in response to the rising edge > > + of the signal > > + bit[11] - LVL = 0, Detects based on the edge > > + bits[12:14] - AM = 2, Bus cycle mode > > + bit[15] - TM = 0, Single transfer mode > > I wish there was better solution to this. Device tree sources are quite human-readable, this really is > not. > Do agree! Cheers, Prabhakar
Hi Pavel, > Subject: Re: [PATCH 5.10.y-cip 04/31] ASoC: dt-bindings: renesas,rz-ssi: > Update slave dma channel configuration parameter > > Hi! > > > From: Biju Das <biju.das.jz@bp.renesas.com> > > > > commit bed0b1c1e88a27b76c74584128cadebc6fa58622 upstream. > > > > The DMAC on RZ/G2L has specific slave channel configuration parameters > > for SSI. > > This patch updates the dmas description and example node to include > > the encoded slave channel configuration. > > > +++ b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml > > @@ -48,6 +48,24 @@ properties: > > dmas: > > minItems: 1 > > maxItems: 2 > > + description: > > + The first cell represents a phandle to dmac > > + The second cell specifies the encoded MID/RID values of the SSI > port > > + connected to the DMA client and the slave channel configuration > > + parameters. > > + bits[0:9] - Specifies MID/RID value of a SSI channel as below > > + MID/RID value of SSI rx0 = 0x256 > > + MID/RID value of SSI tx0 = 0x255 > > + MID/RID value of SSI rx1 = 0x25a > > + MID/RID value of SSI tx1 = 0x259 > > + MID/RID value of SSI rt2 = 0x25f > > + MID/RID value of SSI rx3 = 0x262 > > + MID/RID value of SSI tx3 = 0x261 > > + bit[10] - HIEN = 1, Detects a request in response to the > rising edge > > + of the signal > > + bit[11] - LVL = 0, Detects based on the edge > > + bits[12:14] - AM = 2, Bus cycle mode > > + bit[15] - TM = 0, Single transfer mode > > I wish there was better solution to this. Device tree sources are quite > human-readable, this really is not. Can you please suggest the better solution? Cheers, Biju
diff --git a/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml index 471937cb8d05..414ff8035a4e 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,rz-ssi.yaml @@ -48,6 +48,24 @@ properties: dmas: minItems: 1 maxItems: 2 + description: + The first cell represents a phandle to dmac + The second cell specifies the encoded MID/RID values of the SSI port + connected to the DMA client and the slave channel configuration + parameters. + bits[0:9] - Specifies MID/RID value of a SSI channel as below + MID/RID value of SSI rx0 = 0x256 + MID/RID value of SSI tx0 = 0x255 + MID/RID value of SSI rx1 = 0x25a + MID/RID value of SSI tx1 = 0x259 + MID/RID value of SSI rt2 = 0x25f + MID/RID value of SSI rx3 = 0x262 + MID/RID value of SSI tx3 = 0x261 + bit[10] - HIEN = 1, Detects a request in response to the rising edge + of the signal + bit[11] - LVL = 0, Detects based on the edge + bits[12:14] - AM = 2, Bus cycle mode + bit[15] - TM = 0, Single transfer mode dma-names: oneOf: @@ -93,8 +111,8 @@ examples: clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; power-domains = <&cpg>; resets = <&cpg R9A07G044_SSI0_RST_M2_REG>; - dmas = <&dmac 0x255>, - <&dmac 0x256>; + dmas = <&dmac 0x2655>, + <&dmac 0x2656>; dma-names = "tx", "rx"; #sound-dai-cells = <0>; };