| Message ID | 20220729111116.259146-1-conor.dooley@microchip.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | c45fc916c2b2cc2a0587659c18d6ceef9b7299be |
| Delegated to: | Palmer Dabbelt |
| Headers | show |
| Series | riscv: enable software resend of irqs | expand |
Conor Dooley <conor.dooley@microchip.com> writes: > The PLIC specification does not describe the interrupt pendings bits as > read-write, only that they "can be read". To allow for retriggering of > interrupts (and the use of the irq debugfs interface) enable > HARDIRQS_SW_RESEND for RISC-V. > > Link: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-pending-bits > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Waking up an old thread. FWIW, Reviewed-by: Björn Töpel <bjorn@kernel.org>
On Mon, 10 Oct 2022 04:21:38 PDT (-0700), bjorn@kernel.org wrote: > Conor Dooley <conor.dooley@microchip.com> writes: > >> The PLIC specification does not describe the interrupt pendings bits as >> read-write, only that they "can be read". To allow for retriggering of >> interrupts (and the use of the irq debugfs interface) enable >> HARDIRQS_SW_RESEND for RISC-V. >> >> Link: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-pending-bits >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > Waking up an old thread. FWIW, > > Reviewed-by: Björn Töpel <bjorn@kernel.org> Thanks. This look reasonable to me, not sure if the irqchip folks have an opinion though? In theory the PLIC isn't the only interrupt controller (and that spec predates most of the implementations), but the SiFive PLIC derived interrupt controllers have become a defacto standard and IIRC they're the only thing shipping right now so I think it's OK to just stick this in arch code. We could mark it as "if SIFIVE_PLIC" or something, but I don't know if that's worth doing. Either way, this isn't really my thing. Happy to take it via the RISC-V tree, but Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Tested-by: Palmer Dabbelt <palmer@rivosinc.com> # on QEMU if you want it via the irqchip tree. I put it over at palmer/riscv-irq_sw_resend in case you want to do a shared tree or something, but that seems pretty overkill to me here. It's passing all my tests, but that's just QEMU.
On Thu, 13 Oct 2022 02:13:50 +0100, Palmer Dabbelt <palmer@dabbelt.com> wrote: > > On Mon, 10 Oct 2022 04:21:38 PDT (-0700), bjorn@kernel.org wrote: > > Conor Dooley <conor.dooley@microchip.com> writes: > > > >> The PLIC specification does not describe the interrupt pendings bits as > >> read-write, only that they "can be read". To allow for retriggering of > >> interrupts (and the use of the irq debugfs interface) enable > >> HARDIRQS_SW_RESEND for RISC-V. > >> > >> Link: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-pending-bits > >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > > > Waking up an old thread. FWIW, > > > > Reviewed-by: Björn Töpel <bjorn@kernel.org> > > Thanks. This look reasonable to me, not sure if the irqchip folks > have an opinion though? > > In theory the PLIC isn't the only interrupt controller (and that spec > predates most of the implementations), but the SiFive PLIC derived > interrupt controllers have become a defacto standard and IIRC they're > the only thing shipping right now so I think it's OK to just stick > this in arch code. We could mark it as "if SIFIVE_PLIC" or something, > but I don't know if that's worth doing. Setting it at the architecture level is at least consistent with what other arches are doing. If we need to fix it one day, we'll do it globally. > > Either way, this isn't really my thing. Happy to take it via the > RISC-V tree, but > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > Tested-by: Palmer Dabbelt <palmer@rivosinc.com> # on QEMU Please take it directly, and feel free to add my Acked-by: Marc Zyngier <maz@kernel.org> to it. Thanks, M.
On Fri, 29 Jul 2022 12:11:17 +0100, Conor Dooley wrote: > The PLIC specification does not describe the interrupt pendings bits as > read-write, only that they "can be read". To allow for retriggering of > interrupts (and the use of the irq debugfs interface) enable > HARDIRQS_SW_RESEND for RISC-V. > > Applied, thanks! [1/1] riscv: enable software resend of irqs https://git.kernel.org/palmer/c/c45fc916c2b2 Best regards,
On Thu, 13 Oct 2022 03:20:00 PDT (-0700), Marc Zyngier wrote: > On Thu, 13 Oct 2022 02:13:50 +0100, > Palmer Dabbelt <palmer@dabbelt.com> wrote: >> >> On Mon, 10 Oct 2022 04:21:38 PDT (-0700), bjorn@kernel.org wrote: >> > Conor Dooley <conor.dooley@microchip.com> writes: >> > >> >> The PLIC specification does not describe the interrupt pendings bits as >> >> read-write, only that they "can be read". To allow for retriggering of >> >> interrupts (and the use of the irq debugfs interface) enable >> >> HARDIRQS_SW_RESEND for RISC-V. >> >> >> >> Link: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-pending-bits >> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >> > >> > Waking up an old thread. FWIW, >> > >> > Reviewed-by: Björn Töpel <bjorn@kernel.org> >> >> Thanks. This look reasonable to me, not sure if the irqchip folks >> have an opinion though? >> >> In theory the PLIC isn't the only interrupt controller (and that spec >> predates most of the implementations), but the SiFive PLIC derived >> interrupt controllers have become a defacto standard and IIRC they're >> the only thing shipping right now so I think it's OK to just stick >> this in arch code. We could mark it as "if SIFIVE_PLIC" or something, >> but I don't know if that's worth doing. > > Setting it at the architecture level is at least consistent with what > other arches are doing. If we need to fix it one day, we'll do it > globally. Works for me. > >> >> Either way, this isn't really my thing. Happy to take it via the >> RISC-V tree, but >> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> >> Tested-by: Palmer Dabbelt <palmer@rivosinc.com> # on QEMU > > Please take it directly, and feel free to add my > > Acked-by: Marc Zyngier <maz@kernel.org> > > to it. Thanks, it's on riscv/for-next. > > Thanks, > > M. > > -- > Without deviation from the norm, progress is not possible.
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 55d2cc458ace..d8a132426c64 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -69,6 +69,7 @@ config RISCV select GENERIC_SMP_IDLE_THREAD select GENERIC_TIME_VSYSCALL if MMU && 64BIT select GENERIC_VDSO_TIME_NS if HAVE_GENERIC_VDSO + select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL select HAVE_ARCH_JUMP_LABEL_RELATIVE if !XIP_KERNEL
The PLIC specification does not describe the interrupt pendings bits as read-write, only that they "can be read". To allow for retriggering of interrupts (and the use of the irq debugfs interface) enable HARDIRQS_SW_RESEND for RISC-V. Link: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-pending-bits Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+)