| Message ID | 20220928131807.30386-1-palmer@rivosinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 5a5294fbe0200d1327f0e089135dad77b45aa2ee |
| Delegated to: | Palmer Dabbelt |
| Headers | show |
| Series | RISC-V: Re-enable counter access from userspace | expand |
On Wed, Sep 28, 2022 at 06:18:07AM -0700, Palmer Dabbelt wrote: > These counters were part of the ISA when we froze the uABI, removing > them breaks userspace. > > Link: https://lore.kernel.org/all/YxEhC%2FmDW1lFt36J@aurel32.net/ > Fixes: e9991434596f ("RISC-V: Add perf platform driver based on SBI PMU extension") At the risk of stating the obvious, I assume this will also be CC:stable when you apply it since this goes back as far as (I think) 5.18? Thanks, Conor. > Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> > --- > drivers/perf/riscv_pmu_sbi.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > index 6f6681bbfd36..e45daffbfb36 100644 > --- a/drivers/perf/riscv_pmu_sbi.c > +++ b/drivers/perf/riscv_pmu_sbi.c > @@ -645,8 +645,11 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) > struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node); > struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); > > - /* Enable the access for TIME csr only from the user mode now */ > - csr_write(CSR_SCOUNTEREN, 0x2); > + /* > + * Enable the access for CYCLE, TIME, and INSTRET CSRs from userspace, > + * as is necessary to maintain uABI compatibility. > + */ > + csr_write(CSR_SCOUNTEREN, 0x7); > > /* Stop all the counters so that they can be enabled from perf */ > pmu_sbi_stop_all(pmu); > -- > 2.34.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Wed, Sep 28, 2022 at 06:18:07AM -0700, Palmer Dabbelt wrote: > These counters were part of the ISA when we froze the uABI, removing > them breaks userspace. > > Link: https://lore.kernel.org/all/YxEhC%2FmDW1lFt36J@aurel32.net/ > Fixes: e9991434596f ("RISC-V: Add perf platform driver based on SBI PMU extension") > Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Completely forgot about this and was wondering why my timer accessing, userspace program was not working on an unmatched but did on an icicle... This patch makes it work again :) Tested-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > --- > drivers/perf/riscv_pmu_sbi.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > index 6f6681bbfd36..e45daffbfb36 100644 > --- a/drivers/perf/riscv_pmu_sbi.c > +++ b/drivers/perf/riscv_pmu_sbi.c > @@ -645,8 +645,11 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) > struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node); > struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); > > - /* Enable the access for TIME csr only from the user mode now */ > - csr_write(CSR_SCOUNTEREN, 0x2); > + /* > + * Enable the access for CYCLE, TIME, and INSTRET CSRs from userspace, > + * as is necessary to maintain uABI compatibility. > + */ > + csr_write(CSR_SCOUNTEREN, 0x7); > > /* Stop all the counters so that they can be enabled from perf */ > pmu_sbi_stop_all(pmu); > -- > 2.34.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Wed, 28 Sep 2022 06:18:07 -0700, Palmer Dabbelt wrote: > These counters were part of the ISA when we froze the uABI, removing > them breaks userspace. > > Applied, thanks! [1/1] RISC-V: Re-enable counter access from userspace https://git.kernel.org/palmer/c/5a5294fbe020 Best regards,
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 6f6681bbfd36..e45daffbfb36 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -645,8 +645,11 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node); struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); - /* Enable the access for TIME csr only from the user mode now */ - csr_write(CSR_SCOUNTEREN, 0x2); + /* + * Enable the access for CYCLE, TIME, and INSTRET CSRs from userspace, + * as is necessary to maintain uABI compatibility. + */ + csr_write(CSR_SCOUNTEREN, 0x7); /* Stop all the counters so that they can be enabled from perf */ pmu_sbi_stop_all(pmu);
These counters were part of the ISA when we froze the uABI, removing them breaks userspace. Link: https://lore.kernel.org/all/YxEhC%2FmDW1lFt36J@aurel32.net/ Fixes: e9991434596f ("RISC-V: Add perf platform driver based on SBI PMU extension") Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> --- drivers/perf/riscv_pmu_sbi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)