| Message ID | 20221017085525.3898649-1-andrzej.hajda@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: fix clear mask in GEN7_MISCCPCTL update | expand |
On Mon, Oct 17, 2022 at 10:55:25AM +0200, Andrzej Hajda wrote: >GEN7_DOP_CLOCK_GATE_ENABLE bit should be cleared, not inverse. >The bug was introduced during conversion to intel_uncore_rmw helper. > >Suggested-by: Matt Roper <matthew.d.roper@intel.com> >Fixes: 8cee664d3eb6f8 ("drm/i915: use proper helper for register updates") >Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Lucas De Marchi
On Mon, Oct 17, 2022 at 10:22:08AM -0700, Lucas De Marchi wrote: >On Mon, Oct 17, 2022 at 10:55:25AM +0200, Andrzej Hajda wrote: >>GEN7_DOP_CLOCK_GATE_ENABLE bit should be cleared, not inverse. >>The bug was introduced during conversion to intel_uncore_rmw helper. >> >>Suggested-by: Matt Roper <matthew.d.roper@intel.com> >>Fixes: 8cee664d3eb6f8 ("drm/i915: use proper helper for register updates") >>Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> > > >Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> and pushed thanks Lucas De Marchi
On Mon, Oct 17, 2022 at 10:55:25AM +0200, Andrzej Hajda wrote: > GEN7_DOP_CLOCK_GATE_ENABLE bit should be cleared, not inverse. > The bug was introduced during conversion to intel_uncore_rmw helper. > > Suggested-by: Matt Roper <matthew.d.roper@intel.com> > Fixes: 8cee664d3eb6f8 ("drm/i915: use proper helper for register updates") > Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 4 ++-- > drivers/gpu/drm/i915/intel_pm.c | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 2b75ca5e6e618b..d68859866bf238 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1052,8 +1052,8 @@ static void ivb_parity_work(struct work_struct *work) > if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) > goto out; > > - misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, ~GEN7_DOP_CLOCK_GATE_ENABLE, > - 0); > + misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, > + GEN7_DOP_CLOCK_GATE_ENABLE, 0); > intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL); > > while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 9f6c58ad8bdb06..19d4a88184d7a1 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4321,8 +4321,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, > u32 val; > > /* WaTempDisableDOPClkGating:bdw */ > - misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, ~GEN7_DOP_CLOCK_GATE_ENABLE, > - 0); > + misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, > + GEN7_DOP_CLOCK_GATE_ENABLE, 0); > > val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1); > val &= ~L3_PRIO_CREDITS_MASK; > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 2b75ca5e6e618b..d68859866bf238 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1052,8 +1052,8 @@ static void ivb_parity_work(struct work_struct *work) if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) goto out; - misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, ~GEN7_DOP_CLOCK_GATE_ENABLE, - 0); + misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, + GEN7_DOP_CLOCK_GATE_ENABLE, 0); intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL); while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9f6c58ad8bdb06..19d4a88184d7a1 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4321,8 +4321,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, u32 val; /* WaTempDisableDOPClkGating:bdw */ - misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, ~GEN7_DOP_CLOCK_GATE_ENABLE, - 0); + misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, + GEN7_DOP_CLOCK_GATE_ENABLE, 0); val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1); val &= ~L3_PRIO_CREDITS_MASK;
GEN7_DOP_CLOCK_GATE_ENABLE bit should be cleared, not inverse. The bug was introduced during conversion to intel_uncore_rmw helper. Suggested-by: Matt Roper <matthew.d.roper@intel.com> Fixes: 8cee664d3eb6f8 ("drm/i915: use proper helper for register updates") Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 4 ++-- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)