| Message ID | 20221101052049.3946283-2-thippeswamy.havalige@amd.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | [v2,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge | expand |
On Tue, 01 Nov 2022 10:50:49 +0530, Thippeswamy Havalige wrote: > Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge > dt binding. > > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> > --- > .../bindings/pci/xilinx-nwl-pcie.txt | 73 ---------- > .../bindings/pci/xlnx,nwl-pcie.yaml | 137 ++++++++++++++++++ > 2 files changed, 137 insertions(+), 73 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt > create mode 100644 Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/patch/ pcie@fd0e0000: Unevaluated properties are not allowed ('iommus', 'power-domains' were unexpected) arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dtb arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dtb arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dtb arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dtb arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dtb arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dtb arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dtb arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dtb arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dtb arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dtb
Hi Rob, Accepted the review comments and ll update the patch and send those again. Regards, Thippeswamy H > -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: Tuesday, November 1, 2022 5:26 PM > To: Havalige, Thippeswamy <thippeswamy.havalige@amd.com> > Cc: robh+dt@kernel.org; bhelgaas@google.com; michals@xilinx.com; > krzysztof.kozlowski@linaro.org; linux-kernel@vger.kernel.org; Yeleswarapu, > Nagaradhesh <nagaradhesh.yeleswarapu@amd.com>; linux- > pci@vger.kernel.org; Gogada, Bharat Kumar > <bharat.kumar.gogada@amd.com>; devicetree@vger.kernel.org > Subject: Re: [PATCH v2 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML > schemas of Xilinx NWL PCIe Root Port Bridge > > > On Tue, 01 Nov 2022 10:50:49 +0530, Thippeswamy Havalige wrote: > > Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge dt > > binding. > > > > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> > > --- > > .../bindings/pci/xilinx-nwl-pcie.txt | 73 ---------- > > .../bindings/pci/xlnx,nwl-pcie.yaml | 137 ++++++++++++++++++ > > 2 files changed, 137 insertions(+), 73 deletions(-) delete mode > > 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt > > create mode 100644 > > Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > > > > Running 'make dtbs_check' with the schema in this patch gives the following > warnings. Consider if they are expected or the schema is incorrect. These > may not be new warnings. > > Note that it is not yet a requirement to have 0 warnings for dtbs_check. > This will change in the future. > > Full log is available here: https://patchwork.ozlabs.org/patch/ > > > pcie@fd0e0000: Unevaluated properties are not allowed ('iommus', 'power- > domains' were unexpected) > arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dtb > arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dtb > arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dtb > arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dtb
On 01/11/2022 01:20, Thippeswamy Havalige wrote: > Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge > dt binding. > > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> > --- > .../bindings/pci/xilinx-nwl-pcie.txt | 73 ---------- > .../bindings/pci/xlnx,nwl-pcie.yaml | 137 ++++++++++++++++++ > 2 files changed, 137 insertions(+), 73 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt > create mode 100644 Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt > deleted file mode 100644 > index f56f8c58c5d9..000000000000 > --- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt > +++ /dev/null > @@ -1,73 +0,0 @@ > -* Xilinx NWL PCIe Root Port Bridge DT description > - > -Required properties: > -- compatible: Should contain "xlnx,nwl-pcie-2.11" > -- #address-cells: Address representation for root ports, set to <3> > -- #size-cells: Size representation for root ports, set to <2> > -- #interrupt-cells: specifies the number of cells needed to encode an > - interrupt source. The value must be 1. > -- reg: Should contain Bridge, PCIe Controller registers location, > - configuration space, and length > -- reg-names: Must include the following entries: > - "breg": bridge registers > - "pcireg": PCIe controller registers > - "cfg": configuration space region > -- device_type: must be "pci" > -- interrupts: Should contain NWL PCIe interrupt > -- interrupt-names: Must include the following entries: > - "msi1, msi0": interrupt asserted when an MSI is received > - "intx": interrupt asserted when a legacy interrupt is received > - "misc": interrupt asserted when miscellaneous interrupt is received > -- interrupt-map-mask and interrupt-map: standard PCI properties to define the > - mapping of the PCI interface to interrupt numbers. > -- ranges: ranges for the PCI memory regions (I/O space region is not > - supported by hardware) > - Please refer to the standard PCI bus binding document for a more > - detailed explanation > -- msi-controller: indicates that this is MSI controller node > -- msi-parent: MSI parent of the root complex itself > -- legacy-interrupt-controller: Interrupt controller device node for Legacy > - interrupts > - - interrupt-controller: identifies the node as an interrupt controller > - - #interrupt-cells: should be set to 1 > - - #address-cells: specifies the number of cells needed to encode an > - address. The value must be 0. > - > -Optional properties: > -- dma-coherent: present if DMA operations are coherent > -- clocks: Input clock specifier. Refer to common clock bindings > - > -Example: > -++++++++ > - > -nwl_pcie: pcie@fd0e0000 { > - #address-cells = <3>; > - #size-cells = <2>; > - compatible = "xlnx,nwl-pcie-2.11"; > - #interrupt-cells = <1>; > - msi-controller; > - device_type = "pci"; > - interrupt-parent = <&gic>; > - interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>; > - interrupt-names = "msi0", "msi1", "intx", "dummy", "misc"; > - interrupt-map-mask = <0x0 0x0 0x0 0x7>; > - interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, > - <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, > - <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, > - <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; > - > - msi-parent = <&nwl_pcie>; > - reg = <0x0 0xfd0e0000 0x0 0x1000>, > - <0x0 0xfd480000 0x0 0x1000>, > - <0x80 0x00000000 0x0 0x1000000>; > - reg-names = "breg", "pcireg", "cfg"; > - ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ > - 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ > - > - pcie_intc: legacy-interrupt-controller { > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <1>; > - }; > - > -}; > diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > new file mode 100644 > index 000000000000..f6634be618a2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > @@ -0,0 +1,137 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx NWL PCIe Root Port Bridge > + > +maintainers: > + - Thippeswamy Havalige <thippeswamy.havalige@amd.com> > + > +allOf: > + - $ref: /schemas/pci/pci-bus.yaml# > + - $ref: /schemas/interrupt-controller/msi-controller.yaml# > + > +properties: > + compatible: > + const: xlnx,nwl-pcie-2.11 > + > + reg: > + items: > + - description: PCIe bridge registers location. > + - description: PCIe Controller registers location. > + - description: PCIe Configuration space region. > + > + reg-names: > + items: > + - const: breg const: bridge > + - const: pcireg const: pci > + - const: cfg > + > + interrupts: > + items: > + - description: msi0 interrupt asserted when an MSI is received > + - description: msi1 interrupt asserted when an MSI is received > + - description: interrupt asserted when a legacy interrupt is received > + - description: unused interrupt(dummy) > + - description: interrupt asserted when miscellaneous interrupt is received > + > + interrupt-names: > + maxItems: 5 I didn't notice last time - what are the names? They need to be defined. > + > + interrupt-map-mask: > + items: > + - const: 0 > + - const: 0 > + - const: 0 > + - const: 7 > + Best regards, Krzysztof
> -----Original Message----- > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Sent: Wednesday, November 2, 2022 8:53 PM > To: Havalige, Thippeswamy <thippeswamy.havalige@amd.com>; linux- > pci@vger.kernel.org; linux-kernel@vger.kernel.org; > devicetree@vger.kernel.org > Cc: bhelgaas@google.com; michals@xilinx.com; robh+dt@kernel.org; > Yeleswarapu, Nagaradhesh <nagaradhesh.yeleswarapu@amd.com>; > Gogada, Bharat Kumar <bharat.kumar.gogada@amd.com> > Subject: Re: [PATCH v2 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML > schemas of Xilinx NWL PCIe Root Port Bridge > > On 01/11/2022 01:20, Thippeswamy Havalige wrote: > > Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge dt > > binding. > > > > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> > > --- > > .../bindings/pci/xilinx-nwl-pcie.txt | 73 ---------- > > .../bindings/pci/xlnx,nwl-pcie.yaml | 137 ++++++++++++++++++ > > 2 files changed, 137 insertions(+), 73 deletions(-) delete mode > > 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt > > create mode 100644 > > Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > > > > diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt > > b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt > > deleted file mode 100644 > > index f56f8c58c5d9..000000000000 > > --- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt > > +++ /dev/null > > @@ -1,73 +0,0 @@ > > -* Xilinx NWL PCIe Root Port Bridge DT description > > - > > -Required properties: > > -- compatible: Should contain "xlnx,nwl-pcie-2.11" > > -- #address-cells: Address representation for root ports, set to <3> > > -- #size-cells: Size representation for root ports, set to <2> > > -- #interrupt-cells: specifies the number of cells needed to encode an > > - interrupt source. The value must be 1. > > -- reg: Should contain Bridge, PCIe Controller registers location, > > - configuration space, and length > > -- reg-names: Must include the following entries: > > - "breg": bridge registers > > - "pcireg": PCIe controller registers > > - "cfg": configuration space region > > -- device_type: must be "pci" > > -- interrupts: Should contain NWL PCIe interrupt > > -- interrupt-names: Must include the following entries: > > - "msi1, msi0": interrupt asserted when an MSI is received > > - "intx": interrupt asserted when a legacy interrupt is received > > - "misc": interrupt asserted when miscellaneous interrupt is received > > -- interrupt-map-mask and interrupt-map: standard PCI properties to > define the > > - mapping of the PCI interface to interrupt numbers. > > -- ranges: ranges for the PCI memory regions (I/O space region is not > > - supported by hardware) > > - Please refer to the standard PCI bus binding document for a more > > - detailed explanation > > -- msi-controller: indicates that this is MSI controller node > > -- msi-parent: MSI parent of the root complex itself > > -- legacy-interrupt-controller: Interrupt controller device node for Legacy > > - interrupts > > - - interrupt-controller: identifies the node as an interrupt controller > > - - #interrupt-cells: should be set to 1 > > - - #address-cells: specifies the number of cells needed to encode an > > - address. The value must be 0. > > - > > -Optional properties: > > -- dma-coherent: present if DMA operations are coherent > > -- clocks: Input clock specifier. Refer to common clock bindings > > - > > -Example: > > -++++++++ > > - > > -nwl_pcie: pcie@fd0e0000 { > > - #address-cells = <3>; > > - #size-cells = <2>; > > - compatible = "xlnx,nwl-pcie-2.11"; > > - #interrupt-cells = <1>; > > - msi-controller; > > - device_type = "pci"; > > - interrupt-parent = <&gic>; > > - interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>; > > - interrupt-names = "msi0", "msi1", "intx", "dummy", "misc"; > > - interrupt-map-mask = <0x0 0x0 0x0 0x7>; > > - interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, > > - <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, > > - <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, > > - <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; > > - > > - msi-parent = <&nwl_pcie>; > > - reg = <0x0 0xfd0e0000 0x0 0x1000>, > > - <0x0 0xfd480000 0x0 0x1000>, > > - <0x80 0x00000000 0x0 0x1000000>; > > - reg-names = "breg", "pcireg", "cfg"; > > - ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 > 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ > > - 0x43000000 0x00000006 0x00000000 0x00000006 > 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ > > - > > - pcie_intc: legacy-interrupt-controller { > > - interrupt-controller; > > - #address-cells = <0>; > > - #interrupt-cells = <1>; > > - }; > > - > > -}; > > diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > > b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > > new file mode 100644 > > index 000000000000..f6634be618a2 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > > @@ -0,0 +1,137 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Xilinx NWL PCIe Root Port Bridge > > + > > +maintainers: > > + - Thippeswamy Havalige <thippeswamy.havalige@amd.com> > > + > > +allOf: > > + - $ref: /schemas/pci/pci-bus.yaml# > > + - $ref: /schemas/interrupt-controller/msi-controller.yaml# > > + > > +properties: > > + compatible: > > + const: xlnx,nwl-pcie-2.11 > > + > > + reg: > > + items: > > + - description: PCIe bridge registers location. > > + - description: PCIe Controller registers location. > > + - description: PCIe Configuration space region. > > + > > + reg-names: > > + items: > > + - const: breg > > const: bridge > > > + - const: pcireg > > const: pci These reg-names are used in driver and existing customers are using these reg-names. Please let me know why reg-names need to be changed ? > > + - const: cfg > > + > > + interrupts: > > + items: > > + - description: msi0 interrupt asserted when an MSI is received > > + - description: msi1 interrupt asserted when an MSI is received > > + - description: interrupt asserted when a legacy interrupt is received > > + - description: unused interrupt(dummy) > > + - description: interrupt asserted when miscellaneous interrupt > > + is received > > + > > + interrupt-names: > > + maxItems: 5 > > I didn't notice last time - what are the names? They need to be defined. > > > + > > + interrupt-map-mask: > > + items: > > + - const: 0 > > + - const: 0 > > + - const: 0 > > + - const: 7 > > + > > Best regards, > Krzysztof
On 03/11/2022 04:59, Havalige, Thippeswamy wrote: >> -----Original Message----- >> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> Sent: Wednesday, November 2, 2022 8:53 PM >> To: Havalige, Thippeswamy <thippeswamy.havalige@amd.com>; linux- >> pci@vger.kernel.org; linux-kernel@vger.kernel.org; >> devicetree@vger.kernel.org >> Cc: bhelgaas@google.com; michals@xilinx.com; robh+dt@kernel.org; >> Yeleswarapu, Nagaradhesh <nagaradhesh.yeleswarapu@amd.com>; >> Gogada, Bharat Kumar <bharat.kumar.gogada@amd.com> >> Subject: Re: [PATCH v2 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML >> schemas of Xilinx NWL PCIe Root Port Bridge >> >> On 01/11/2022 01:20, Thippeswamy Havalige wrote: >>> Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge dt >>> binding. >>> >>> Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> >>> --- >>> .../bindings/pci/xilinx-nwl-pcie.txt | 73 ---------- >>> .../bindings/pci/xlnx,nwl-pcie.yaml | 137 ++++++++++++++++++ >>> 2 files changed, 137 insertions(+), 73 deletions(-) delete mode >>> 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt >>> create mode 100644 >>> Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt >>> b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt >>> deleted file mode 100644 >>> index f56f8c58c5d9..000000000000 >>> --- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt >>> +++ /dev/null >>> @@ -1,73 +0,0 @@ >>> -* Xilinx NWL PCIe Root Port Bridge DT description >>> - >>> -Required properties: >>> -- compatible: Should contain "xlnx,nwl-pcie-2.11" >>> -- #address-cells: Address representation for root ports, set to <3> >>> -- #size-cells: Size representation for root ports, set to <2> >>> -- #interrupt-cells: specifies the number of cells needed to encode an >>> - interrupt source. The value must be 1. >>> -- reg: Should contain Bridge, PCIe Controller registers location, >>> - configuration space, and length >>> -- reg-names: Must include the following entries: >>> - "breg": bridge registers >>> - "pcireg": PCIe controller registers >>> - "cfg": configuration space region >>> -- device_type: must be "pci" >>> -- interrupts: Should contain NWL PCIe interrupt >>> -- interrupt-names: Must include the following entries: >>> - "msi1, msi0": interrupt asserted when an MSI is received >>> - "intx": interrupt asserted when a legacy interrupt is received >>> - "misc": interrupt asserted when miscellaneous interrupt is received >>> -- interrupt-map-mask and interrupt-map: standard PCI properties to >> define the >>> - mapping of the PCI interface to interrupt numbers. >>> -- ranges: ranges for the PCI memory regions (I/O space region is not >>> - supported by hardware) >>> - Please refer to the standard PCI bus binding document for a more >>> - detailed explanation >>> -- msi-controller: indicates that this is MSI controller node >>> -- msi-parent: MSI parent of the root complex itself >>> -- legacy-interrupt-controller: Interrupt controller device node for Legacy >>> - interrupts >>> - - interrupt-controller: identifies the node as an interrupt controller >>> - - #interrupt-cells: should be set to 1 >>> - - #address-cells: specifies the number of cells needed to encode an >>> - address. The value must be 0. >>> - >>> -Optional properties: >>> -- dma-coherent: present if DMA operations are coherent >>> -- clocks: Input clock specifier. Refer to common clock bindings >>> - >>> -Example: >>> -++++++++ >>> - >>> -nwl_pcie: pcie@fd0e0000 { >>> - #address-cells = <3>; >>> - #size-cells = <2>; >>> - compatible = "xlnx,nwl-pcie-2.11"; >>> - #interrupt-cells = <1>; >>> - msi-controller; >>> - device_type = "pci"; >>> - interrupt-parent = <&gic>; >>> - interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>; >>> - interrupt-names = "msi0", "msi1", "intx", "dummy", "misc"; >>> - interrupt-map-mask = <0x0 0x0 0x0 0x7>; >>> - interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, >>> - <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, >>> - <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, >>> - <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; >>> - >>> - msi-parent = <&nwl_pcie>; >>> - reg = <0x0 0xfd0e0000 0x0 0x1000>, >>> - <0x0 0xfd480000 0x0 0x1000>, >>> - <0x80 0x00000000 0x0 0x1000000>; >>> - reg-names = "breg", "pcireg", "cfg"; >>> - ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 >> 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ >>> - 0x43000000 0x00000006 0x00000000 0x00000006 >> 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ >>> - >>> - pcie_intc: legacy-interrupt-controller { >>> - interrupt-controller; >>> - #address-cells = <0>; >>> - #interrupt-cells = <1>; >>> - }; >>> - >>> -}; >>> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml >>> b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml >>> new file mode 100644 >>> index 000000000000..f6634be618a2 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml >>> @@ -0,0 +1,137 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Xilinx NWL PCIe Root Port Bridge >>> + >>> +maintainers: >>> + - Thippeswamy Havalige <thippeswamy.havalige@amd.com> >>> + >>> +allOf: >>> + - $ref: /schemas/pci/pci-bus.yaml# >>> + - $ref: /schemas/interrupt-controller/msi-controller.yaml# >>> + >>> +properties: >>> + compatible: >>> + const: xlnx,nwl-pcie-2.11 >>> + >>> + reg: >>> + items: >>> + - description: PCIe bridge registers location. >>> + - description: PCIe Controller registers location. >>> + - description: PCIe Configuration space region. >>> + >>> + reg-names: >>> + items: >>> + - const: breg >> >> const: bridge >> >>> + - const: pcireg >> >> const: pci > > These reg-names are used in driver and existing customers are using these reg-names. > Please let me know why reg-names need to be changed ? You're right, I missed that this is a conversion... It's fine. > >>> + - const: cfg >>> + >>> + interrupts: >>> + items: >>> + - description: msi0 interrupt asserted when an MSI is received >>> + - description: msi1 interrupt asserted when an MSI is received >>> + - description: interrupt asserted when a legacy interrupt is received >>> + - description: unused interrupt(dummy) >>> + - description: interrupt asserted when miscellaneous interrupt >>> + is received >>> + >>> + interrupt-names: >>> + maxItems: 5 >> >> I didn't notice last time - what are the names? They need to be defined. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt deleted file mode 100644 index f56f8c58c5d9..000000000000 --- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt +++ /dev/null @@ -1,73 +0,0 @@ -* Xilinx NWL PCIe Root Port Bridge DT description - -Required properties: -- compatible: Should contain "xlnx,nwl-pcie-2.11" -- #address-cells: Address representation for root ports, set to <3> -- #size-cells: Size representation for root ports, set to <2> -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. -- reg: Should contain Bridge, PCIe Controller registers location, - configuration space, and length -- reg-names: Must include the following entries: - "breg": bridge registers - "pcireg": PCIe controller registers - "cfg": configuration space region -- device_type: must be "pci" -- interrupts: Should contain NWL PCIe interrupt -- interrupt-names: Must include the following entries: - "msi1, msi0": interrupt asserted when an MSI is received - "intx": interrupt asserted when a legacy interrupt is received - "misc": interrupt asserted when miscellaneous interrupt is received -- interrupt-map-mask and interrupt-map: standard PCI properties to define the - mapping of the PCI interface to interrupt numbers. -- ranges: ranges for the PCI memory regions (I/O space region is not - supported by hardware) - Please refer to the standard PCI bus binding document for a more - detailed explanation -- msi-controller: indicates that this is MSI controller node -- msi-parent: MSI parent of the root complex itself -- legacy-interrupt-controller: Interrupt controller device node for Legacy - interrupts - - interrupt-controller: identifies the node as an interrupt controller - - #interrupt-cells: should be set to 1 - - #address-cells: specifies the number of cells needed to encode an - address. The value must be 0. - -Optional properties: -- dma-coherent: present if DMA operations are coherent -- clocks: Input clock specifier. Refer to common clock bindings - -Example: -++++++++ - -nwl_pcie: pcie@fd0e0000 { - #address-cells = <3>; - #size-cells = <2>; - compatible = "xlnx,nwl-pcie-2.11"; - #interrupt-cells = <1>; - msi-controller; - device_type = "pci"; - interrupt-parent = <&gic>; - interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>; - interrupt-names = "msi0", "msi1", "intx", "dummy", "misc"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, - <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, - <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, - <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - - msi-parent = <&nwl_pcie>; - reg = <0x0 0xfd0e0000 0x0 0x1000>, - <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; - reg-names = "breg", "pcireg", "cfg"; - ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ - 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ - - pcie_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - -}; diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml new file mode 100644 index 000000000000..f6634be618a2 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx NWL PCIe Root Port Bridge + +maintainers: + - Thippeswamy Havalige <thippeswamy.havalige@amd.com> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + const: xlnx,nwl-pcie-2.11 + + reg: + items: + - description: PCIe bridge registers location. + - description: PCIe Controller registers location. + - description: PCIe Configuration space region. + + reg-names: + items: + - const: breg + - const: pcireg + - const: cfg + + interrupts: + items: + - description: msi0 interrupt asserted when an MSI is received + - description: msi1 interrupt asserted when an MSI is received + - description: interrupt asserted when a legacy interrupt is received + - description: unused interrupt(dummy) + - description: interrupt asserted when miscellaneous interrupt is received + + interrupt-names: + maxItems: 5 + + interrupt-map-mask: + items: + - const: 0 + - const: 0 + - const: 0 + - const: 7 + + "#interrupt-cells": + const: 1 + + msi-controller: + description: Identifies the node as an MSI controller. + + msi-parent: + description: MSI controller the device is capable of using. + + interrupt-map: + maxItems: 4 + + dma-coherent: + description: Optional,present if DMA operations are coherent + + clocks: + description: Optional,Input clock specifier. Refer to common clock bindings + + legacy-interrupt-controller: + description: Interrupt controller node for handling legacy PCI interrupts. + type: object + properties: + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + "interrupt-controller": true + + required: + - '#address-cells' + - '#interrupt-cells' + - interrupt-controller + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - "#interrupt-cells" + - interrupt-map + - interrupt-map-mask + - msi-controller + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + nwl_pcie: pcie@fd0e0000 { + compatible = "xlnx,nwl-pcie-2.11"; + reg = <0x0 0xfd0e0000 0x0 0x1000>, + <0x0 0xfd480000 0x0 0x1000>, + <0x80 0x00000000 0x0 0x1000000>; + reg-names = "breg", "pcireg", "cfg"; + ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, + <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + msi-controller; + device_type = "pci"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "intx", "dummy", "misc"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; + msi-parent = <&nwl_pcie>; + pcie_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + };
Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge dt binding. Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> --- .../bindings/pci/xilinx-nwl-pcie.txt | 73 ---------- .../bindings/pci/xlnx,nwl-pcie.yaml | 137 ++++++++++++++++++ 2 files changed, 137 insertions(+), 73 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml