| Message ID | 20230203081807.2248625-10-abel.vesa@linaro.org (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Delegated to: | Rob Herring |
| Headers | show |
| Series | sm8550: Add PCIe HC and PHY support | expand |
On Fri, Feb 03, 2023 at 10:18:04AM +0200, Abel Vesa wrote: > Add the SM8550 platform to the binding. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
On Fri, Feb 03, 2023 at 10:18:04AM +0200, Abel Vesa wrote: > Add the SM8550 platform to the binding. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > > This patchset relies on the following patchset: > https://lore.kernel.org/all/20230117224148.1914627-1-abel.vesa@linaro.org/ > > The v6 of this patch is: > https://lore.kernel.org/all/20230202123902.3831491-10-abel.vesa@linaro.org/ > > Changes since v6: > * none > > Changes since v5: > * added Krzysztof's R-b tag > > Changes since v4: > * dropped _serdes infix from ln_shrd table name and from every ln_shrd > variable name > * added hyphen between "no CSR" in both places > * dropped has_ln_shrd_serdes_tbl > * reordered qmp_pcie_offsets_v6_20 by struct members > * added rollback for no-CSR reset in qmp_pcie_init fail path > * moved ln_shrd offset calculation after port_b > * dropped the minItems for interconnects > * made iommu related properties global > * renamed noc_aggr_4 back to noc_aggr > > Changes since v3: > * renamed noc_aggr to noc_aggr_4, as found in the driver > > Changes since v2: > * dropped the pipe from clock-names > * removed the pcie instance number from aggre clock-names comment > * renamed aggre clock-names to noc_aggr > * dropped the _pcie infix from cnoc_pcie_sf_axi > * renamed pcie_1_link_down_reset to simply link_down > * added enable-gpios back, since pcie1 node will use it > > Changes since v1: > * Switched to single compatible for both PCIes (qcom,pcie-sm8550) > * dropped enable-gpios property > * dropped interconnects related properties, the power-domains > * properties > and resets related properties the sm8550 specific allOf:if:then > * dropped pipe_mux, phy_pipe and ref clocks from the sm8550 specific > allOf:if:then clock-names array and decreased the minItems and > maxItems for clocks property accordingly > * added "minItems: 1" to interconnects, since sm8550 pcie uses just one, > same for interconnect-names > + enable-gpios: > + description: GPIO controlled connection to ENABLE# signal > + maxItems: 1 What is this gpio used for? Describing it as "ENABLE#" looks wrong as AFAIK it's not part of the PCIe interface. There's also no driver support being adding for this gpio as part of this series and you don't use it for either controller on the MTP. Are you relying on firmware to enable this one currently perhaps? > + > perst-gpios: > description: GPIO controlled connection to PERST# signal > maxItems: 1 Johan
On 23-02-03 11:03:05, Johan Hovold wrote: > On Fri, Feb 03, 2023 at 10:18:04AM +0200, Abel Vesa wrote: > > Add the SM8550 platform to the binding. > > > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > --- > > > > This patchset relies on the following patchset: > > https://lore.kernel.org/all/20230117224148.1914627-1-abel.vesa@linaro.org/ > > > > The v6 of this patch is: > > https://lore.kernel.org/all/20230202123902.3831491-10-abel.vesa@linaro.org/ > > > > Changes since v6: > > * none > > > > Changes since v5: > > * added Krzysztof's R-b tag > > > > Changes since v4: > > * dropped _serdes infix from ln_shrd table name and from every ln_shrd > > variable name > > * added hyphen between "no CSR" in both places > > * dropped has_ln_shrd_serdes_tbl > > * reordered qmp_pcie_offsets_v6_20 by struct members > > * added rollback for no-CSR reset in qmp_pcie_init fail path > > * moved ln_shrd offset calculation after port_b > > * dropped the minItems for interconnects > > * made iommu related properties global > > * renamed noc_aggr_4 back to noc_aggr > > > > Changes since v3: > > * renamed noc_aggr to noc_aggr_4, as found in the driver > > > > Changes since v2: > > * dropped the pipe from clock-names > > * removed the pcie instance number from aggre clock-names comment > > * renamed aggre clock-names to noc_aggr > > * dropped the _pcie infix from cnoc_pcie_sf_axi > > * renamed pcie_1_link_down_reset to simply link_down > > * added enable-gpios back, since pcie1 node will use it > > > > Changes since v1: > > * Switched to single compatible for both PCIes (qcom,pcie-sm8550) > > * dropped enable-gpios property > > * dropped interconnects related properties, the power-domains > > * properties > > and resets related properties the sm8550 specific allOf:if:then > > * dropped pipe_mux, phy_pipe and ref clocks from the sm8550 specific > > allOf:if:then clock-names array and decreased the minItems and > > maxItems for clocks property accordingly > > * added "minItems: 1" to interconnects, since sm8550 pcie uses just one, > > same for interconnect-names > > > + enable-gpios: > > + description: GPIO controlled connection to ENABLE# signal > > + maxItems: 1 > > What is this gpio used for? Describing it as "ENABLE#" looks wrong as > AFAIK it's not part of the PCIe interface. Oups, that should've been dropped here as well, as I did in the dts/dtsi patches. > > There's also no driver support being adding for this gpio as part of > this series and you don't use it for either controller on the MTP. > > Are you relying on firmware to enable this one currently perhaps? > > > + > > perst-gpios: > > description: GPIO controlled connection to PERST# signal > > maxItems: 1 > > Johan
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 872817d6d2bd..9f1bdbc4b0fd 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -38,6 +38,7 @@ properties: - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 + - qcom,pcie-sm8550 - items: - const: qcom,pcie-msm8996 - const: qcom,pcie-msm8998 @@ -58,6 +59,12 @@ properties: minItems: 1 maxItems: 8 + iommus: + maxItems: 1 + + iommu-map: + maxItems: 2 + # Common definitions for clocks, clock-names and reset. # Platform constraints are described later. clocks: @@ -108,6 +115,10 @@ properties: power-domains: maxItems: 1 + enable-gpios: + description: GPIO controlled connection to ENABLE# signal + maxItems: 1 + perst-gpios: description: GPIO controlled connection to PERST# signal maxItems: 1 @@ -205,6 +216,7 @@ allOf: - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 + - qcom,pcie-sm8550 then: properties: reg: @@ -639,6 +651,37 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sm8550 + then: + properties: + clocks: + minItems: 7 + maxItems: 8 + clock-names: + minItems: 7 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: noc_aggr # Aggre NoC PCIe AXI clock + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock + resets: + minItems: 1 + maxItems: 2 + reset-names: + minItems: 1 + items: + - const: pci # PCIe core reset + - const: link_down # PCIe link down reset + - if: properties: compatible: @@ -724,6 +767,7 @@ allOf: - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 + - qcom,pcie-sm8550 then: oneOf: - properties: