| Message ID | 20230221083323.302471-11-xingyu.wu@starfivetech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | Add new partial clock and reset drivers for StarFive JH7110 | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes or riscv/for-next |
On Tue, Feb 21, 2023 at 04:33:22PM +0800, Xingyu Wu wrote: > Add DVP and HDMI TX pixel external fixed clocks and the rates are > 74.25MHz and 297MHz. > > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > --- > .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 ++++++++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index c2aa8946a0f1..27af817a55aa 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -86,6 +86,14 @@ &mclk_ext { > clock-frequency = <12288000>; > }; > > +&dvp_clk { > + clock-frequency = <74250000>; > +}; > + > +&hdmitx0_pixelclk { > + clock-frequency = <297000000>; > +}; > + > &uart0 { > pinctrl-names = "default"; > pinctrl-0 = <&uart0_pins>; > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index 005ead2624d4..a5e6fb3ad188 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -245,6 +245,18 @@ mclk_ext: mclk-ext-clock { > #clock-cells = <0>; > }; > > + dvp_clk: dvp-clk-clock { > + compatible = "fixed-clock"; > + clock-output-names = "dvp_clk"; > + #clock-cells = <0>; > + }; > + > + hdmitx0_pixelclk: hdmitx0-pixelclk-clock { > + compatible = "fixed-clock"; > + clock-output-names = "hdmitx0_pixelclk"; > + #clock-cells = <0>; > + }; > + Hmm, would you mind adding these entries with no unit addresses in alphanumerical order? Both in the soc & board dtsi files. Thanks, Conor.
On 2023/2/28 3:55, Conor Dooley wrote: > On Tue, Feb 21, 2023 at 04:33:22PM +0800, Xingyu Wu wrote: >> Add DVP and HDMI TX pixel external fixed clocks and the rates are >> 74.25MHz and 297MHz. >> >> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> >> --- >> .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 ++++++++ >> arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ >> 2 files changed, 20 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> index c2aa8946a0f1..27af817a55aa 100644 >> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> @@ -86,6 +86,14 @@ &mclk_ext { >> clock-frequency = <12288000>; >> }; >> >> +&dvp_clk { >> + clock-frequency = <74250000>; >> +}; >> + >> +&hdmitx0_pixelclk { >> + clock-frequency = <297000000>; >> +}; >> + >> &uart0 { >> pinctrl-names = "default"; >> pinctrl-0 = <&uart0_pins>; >> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi >> index 005ead2624d4..a5e6fb3ad188 100644 >> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi >> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi >> @@ -245,6 +245,18 @@ mclk_ext: mclk-ext-clock { >> #clock-cells = <0>; >> }; >> >> + dvp_clk: dvp-clk-clock { >> + compatible = "fixed-clock"; >> + clock-output-names = "dvp_clk"; >> + #clock-cells = <0>; >> + }; >> + >> + hdmitx0_pixelclk: hdmitx0-pixelclk-clock { >> + compatible = "fixed-clock"; >> + clock-output-names = "hdmitx0_pixelclk"; >> + #clock-cells = <0>; >> + }; >> + > > Hmm, would you mind adding these entries with no unit addresses in > alphanumerical order? Both in the soc & board dtsi files. > Oh, It was my negligence. I will adjust it. Thanks. Best regards, Xingyu Wu
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index c2aa8946a0f1..27af817a55aa 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -86,6 +86,14 @@ &mclk_ext { clock-frequency = <12288000>; }; +&dvp_clk { + clock-frequency = <74250000>; +}; + +&hdmitx0_pixelclk { + clock-frequency = <297000000>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 005ead2624d4..a5e6fb3ad188 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -245,6 +245,18 @@ mclk_ext: mclk-ext-clock { #clock-cells = <0>; }; + dvp_clk: dvp-clk-clock { + compatible = "fixed-clock"; + clock-output-names = "dvp_clk"; + #clock-cells = <0>; + }; + + hdmitx0_pixelclk: hdmitx0-pixelclk-clock { + compatible = "fixed-clock"; + clock-output-names = "hdmitx0_pixelclk"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>;
Add DVP and HDMI TX pixel external fixed clocks and the rates are 74.25MHz and 297MHz. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> --- .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 ++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ 2 files changed, 20 insertions(+)