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[GIT,PULL] RISC-V Devicetrees for v6.4

Message ID 20230406-shank-impromptu-3d483bbc249f@spud (mailing list archive)
State Not Applicable
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Series [GIT,PULL] RISC-V Devicetrees for v6.4 | expand

Pull-request

https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-dt-for-v6.4

Checks

Context Check Description
conchuod/apply fail Pull to for-next failed
conchuod/tree_selection success Pull request for for-next

Message

Conor Dooley April 6, 2023, 8:24 p.m. UTC 
Hey Arnd,

Please pull some Devicetree updates for v6.4, mainly adding the base
level of support for the StarFive VisionFive v2.
I wanted to get an initial PR out before -rc6, but I may have another
PR adding some of the peripherals (pmu, mmc) for the StarFive stuff
that are already reviewed etc, but need a rebase on top of what
actually got applied. Is that okay, or will the end of next week be
too late for you?

As a note, this is against -rc2, rather than -rc1, as I wanted to
apply the StarFive stuff to a branch there'd be a chance of it booting
on for the sake of testing.

Cheers,
Conor.

git request-pull complained that the tag was not present, but I
checked my repo and it is there. ¯\_(ツ)_/¯

The following changes since commit eeac8ede17557680855031c6f305ece2378af326:

  Linux 6.3-rc2 (2023-03-12 16:36:44 -0700)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-dt-for-v6.4

for you to fetch changes up to 4cd4beb98fe5ac2c4bcb995ba6e82322be174abb:

  Merge branch 'riscv-jh7110_initial_dts' into riscv-dt-for-next (2023-04-05 22:23:17 +0100)

----------------------------------------------------------------
RISC-V Devicetrees for v6.4

Microchip:
A "fix" for the system controller's regs on PolarFire SoC, adding a
missing reg property.
The patch had been sitting there for months and I only re-found it
recently, so you can guess how much of a "fix" it actually is. It'll
become needed when the system controller's QSPI gets added in the future,
but at present there's no urgency as the driver can handle both the
current and "fixed" versions.

StarFive:
Basic support for the JH7110 & the associated first-party dev board, the
VisionFive v2 (in two forms). There's a bunch of dt-bindings required
for this too, all of which have had input from the DT folk. There's
enough in this tag to boot to a console w/ an initramfs but little more.
The SoC supports some of the "new" bit manipulation instructions, which
is a good test for the recently added Zbb support in the kernel.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

----------------------------------------------------------------
Conor Dooley (3):
      riscv: dts: microchip: add mpfs specific macb reset support
      riscv: dts: microchip: fix the mpfs' mailbox regs
      Merge branch 'riscv-jh7110_initial_dts' into riscv-dt-for-next

Emil Renner Berthing (6):
      dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
      dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
      dt-bindings: timer: Add StarFive JH7110 clint
      dt-bindings: interrupt-controller: Add StarFive JH7110 plic
      riscv: dts: starfive: Add initial StarFive JH7110 device tree
      riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree

Hal Feng (1):
      dt-bindings: riscv: Add SiFive S7 compatible

Jianlong Huang (1):
      riscv: dts: starfive: Add StarFive JH7110 pin function definitions

 .../bindings/clock/starfive,jh7110-aoncrg.yaml     | 107 +++++
 .../bindings/clock/starfive,jh7110-syscrg.yaml     | 104 +++++
 .../interrupt-controller/sifive,plic-1.0.0.yaml    |   1 +
 Documentation/devicetree/bindings/riscv/cpus.yaml  |   1 +
 .../devicetree/bindings/timer/sifive,clint.yaml    |   1 +
 arch/riscv/boot/dts/microchip/mpfs.dtsi            |  10 +-
 arch/riscv/boot/dts/starfive/Makefile              |   6 +-
 arch/riscv/boot/dts/starfive/jh7110-pinfunc.h      | 308 +++++++++++++
 .../jh7110-starfive-visionfive-2-v1.2a.dts         |  13 +
 .../jh7110-starfive-visionfive-2-v1.3b.dts         |  13 +
 .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 215 +++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi           | 500 +++++++++++++++++++++
 include/dt-bindings/clock/starfive,jh7110-crg.h    | 221 +++++++++
 include/dt-bindings/reset/starfive,jh7110-crg.h    | 154 +++++++
 14 files changed, 1650 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
 create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h
 create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h

Comments

Conor Dooley April 11, 2023, 9:33 p.m. UTC | #1 
On Thu, Apr 06, 2023 at 09:24:40PM +0100, Conor Dooley wrote:

> I may have another
> PR adding some of the peripherals (pmu, mmc) for the StarFive stuff
> that are already reviewed etc, but need a rebase on top of what
> actually got applied. Is that okay, or will the end of next week be
> too late for you?

FWIW, the patches didn't show up yet, and now it is too late for me :)