| Message ID | 20230412110900.69738-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add non-coherent DMA support for AX45MP | expand |
On Wed, Apr 12, 2023 at 12:08:53PM +0100, Prabhakar wrote: > Note, > - This series requires testing on Cores with zicbom and T-Head SoCs As I said last time, I dunno what actual Zicbom stuff exists, other than perhaps the Ventana lads having something. I did some tyre kicking on my D1 and it was fine, although nothing has actually changed materially for either of them with this series in v8.. Cheers, Conor.
On Wed, Apr 12, 2023 at 09:32:30PM +0100, Conor Dooley wrote: > On Wed, Apr 12, 2023 at 12:08:53PM +0100, Prabhakar wrote: > > > Note, > > - This series requires testing on Cores with zicbom and T-Head SoCs > > As I said last time, I dunno what actual Zicbom stuff exists, other than > perhaps the Ventana lads having something. I did some tyre kicking on my > D1 and it was fine, although nothing has actually changed materially for > either of them with this series in v8.. And as saying before, there is absolutely no reason to add non-standard non-coherent DMA support and let this cancer creep. If you want Linux support implement Zicbom, be that in hardware or the SBI.
On Sun, 16 Apr 2023 23:53:17 PDT (-0700), Christoph Hellwig wrote: > On Wed, Apr 12, 2023 at 09:32:30PM +0100, Conor Dooley wrote: >> On Wed, Apr 12, 2023 at 12:08:53PM +0100, Prabhakar wrote: >> >> > Note, >> > - This series requires testing on Cores with zicbom and T-Head SoCs >> >> As I said last time, I dunno what actual Zicbom stuff exists, other than >> perhaps the Ventana lads having something. I did some tyre kicking on my >> D1 and it was fine, although nothing has actually changed materially for >> either of them with this series in v8.. > > And as saying before, there is absolutely no reason to add non-standard > non-coherent DMA support and let this cancer creep. If you want Linux > support implement Zicbom, be that in hardware or the SBI. IMO we should just take the support in Linux: trying to hide stuff behind the SBI leads to more more headaches than it's worth, we end up with a bunch of broken firmware to try and work around. We've already got a mess here because of the D1 support, we might as well just live with it. In practice there's just going to be a ton of mess in arch/riscv, as the ISA has been missing many core features for many years and hardware vendors are allowed to do whatever they want. That's obviously a huge headache, but I think there's nothing we can really do about it.
On Wed, Apr 19, 2023 at 08:59:03AM -0700, Palmer Dabbelt wrote: > IMO we should just take the support in Linux: trying to hide stuff behind the > SBI leads to more more headaches than it's worth, we end up with a bunch of > broken firmware to try and work around. We've already got a mess here because > of the D1 support, we might as well just live with it. I strongly disagree. Adding more and more per-vendor ops simply does not scale. We're getting us into a giant long-time mess that will be unfixable.
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Hi All, non-coherent DMA support for AX45MP ==================================== On the Andes AX45MP core, cache coherency is a specification option so it may not be supported. In this case DMA will fail. To get around with this issue this patch series does the below: 1] Andes alternative ports is implemented as errata which checks if the IOCP is missing and only then applies to CMO errata. One vendor specific SBI EXT (ANDES_SBI_EXT_IOCP_SW_WORKAROUND) is implemented as part of errata. Below are the configs which Andes port provides (and are selected by RZ/Five): - ERRATA_ANDES - ERRATA_ANDES_CMO OpenSBI patch supporting ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI can be found here, https://patchwork.ozlabs.org/project/opensbi/patch/20230317140357.14819-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ 2] Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) block that allows dynamic adjustment of memory attributes in the runtime. It contains a configurable amount of PMA entries implemented as CSR registers to control the attributes of memory locations in interest. OpenSBI configures the PMA regions as required and creates a reserve memory node and propagates it to the higher boot stack. Currently OpenSBI (upstream) configures the required PMA region and passes this a shared DMA pool to Linux. reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; The above shared DMA pool gets appended to Linux DTB so the DMA memory requests go through this region. 3] We provide callbacks to synchronize specific content between memory and cache. 4] RZ/Five SoC selects the below configs - AX45MP_L2_CACHE - DMA_GLOBAL_POOL - ERRATA_ANDES - ERRATA_ANDES_CMO ----------x---------------------x--------------------x---------------x-------------- Note, - This series requires testing on Cores with zicbom and T-Head SoCs - Ive used GCC 12.2.0 for compilation - Tested all the IP blocks on RZ/Five which use DMA - Patch series is dependent on the series from Arnd, https://patchwork.kernel.org/project/linux-riscv/cover/20230327121317.4081816-1-arnd@kernel.org/ - Patches applies on top of palmer/for-next (d34a6b715a23) v7 -> v8 * Dropped using function pointers and switched to ALTERNATIVE_X() * Added new patches (#1, #2) v6 -> v7 * Reworked the code based on Arnd's work * Fixed review comments pointed by Arnd * Fixed review comments pointed by Conor v5.1 -> v6 * Dropped use of ALTERNATIVE_x() macro * Now switched to used function pointers for CMO * Moved driver to drivers/cache folder v5 -> v5.1 * https://patchwork.kernel.org/project/linux-riscv/list/?series=708610&state=%2A&archive=both v4 -> v5 * Rebased ALTERNATIVE_3() macro on top of Andrew's patches * Rebased the changes on top of Heiko's alternative call patches * Dropped configuring the PMA from Linux * Dropped configuring the L2 cache from Linux and dropped the binding for same * Now using runtime patching mechanism instead of compile time config RFC v3 -> v4 * Implemented ALTERNATIVE_3() macro * Now using runtime patching mechanism instead of compile time config * Added Andes CMO as and errata * Fixed comments pointed by Geert RFC v2-> RFC v3 * Fixed review comments pointed by Conor * Move DT binding into cache folder * Fixed DT binding check issue * Added andestech,ax45mp-cache.h header file * Now passing the flags for the PMA setup as part of andestech,pma-regions property. * Added andestech,inst/data-prefetch and andestech,tag/data-ram-ctl properties to configure the L2 cache. * Registered the cache driver as platform driver RFC v1-> RFC v2 * Moved out the code from arc/riscv to drivers/soc/renesas * Now handling the PMA setup as part of the L2 cache * Now making use of dma-noncoherent.c instead SoC specific implementation. * Dropped arch_dma_alloc() and arch_dma_free() * Switched to RISCV_DMA_NONCOHERENT * Included DT binding doc RFC v2: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221003223222.448551-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ RFC v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20220906102154.32526-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar Lad Prabhakar (7): riscv: asm: alternative-macros: Introduce ALTERNATIVE_3() macro riscv: asm: vendorid_list: Add Andes Technology to the vendors list riscv: errata: Add Andes alternative ports dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller cache: Add L2 cache management for Andes AX45MP RISC-V core riscv: errata: Hookup the Andes AX45MP non-coherent handling soc: renesas: Kconfig: Select the required configs for RZ/Five SoC .../cache/andestech,ax45mp-cache.yaml | 81 +++++++ MAINTAINERS | 7 + arch/riscv/Kconfig.errata | 21 ++ arch/riscv/errata/Makefile | 1 + arch/riscv/errata/andes/Makefile | 1 + arch/riscv/errata/andes/errata.c | 104 ++++++++ arch/riscv/include/asm/alternative-macros.h | 51 +++- arch/riscv/include/asm/alternative.h | 3 + arch/riscv/include/asm/cacheflush.h | 9 + arch/riscv/include/asm/errata_list.h | 38 ++- arch/riscv/include/asm/vendorid_list.h | 1 + arch/riscv/kernel/alternative.c | 5 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/cache/Kconfig | 10 + drivers/cache/Makefile | 3 + drivers/cache/ax45mp_cache.c | 222 ++++++++++++++++++ drivers/soc/renesas/Kconfig | 4 + 18 files changed, 552 insertions(+), 12 deletions(-) create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml create mode 100644 arch/riscv/errata/andes/Makefile create mode 100644 arch/riscv/errata/andes/errata.c create mode 100644 drivers/cache/Kconfig create mode 100644 drivers/cache/Makefile create mode 100644 drivers/cache/ax45mp_cache.c