| Message ID | 20230427-fence-blurred-c92fb69d4137@wendy (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [v1] dt-bindings: riscv: explicitly mention assumption of Zicsr & Zifencei support | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Single patches do not need cover letters |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD b09313dd2e72 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 1 and now 1 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 18 this patch: 18 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 18 this patch: 18 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 12 lines checked |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Thu, 27 Apr 2023 11:43:42 +0100, Conor Dooley wrote: > The dt-binding was defined before the extraction of csr access and > fence.i into their own extensions, and thus the presence of the I > base extension implies Zicsr and Zifencei. > There's no harm in adding them obviously, but for backwards > compatibility with DTs that existed prior to that extraction, software > is unable to differentiate between "i" and "i_zicsr_zifencei" without > any further information. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > CC: Conor Dooley <conor@kernel.org> > CC: Rob Herring <robh+dt@kernel.org> > CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> > CC: Paul Walmsley <paul.walmsley@sifive.com> > CC: Palmer Dabbelt <palmer@dabbelt.com> > CC: linux-riscv@lists.infradead.org > CC: devicetree@vger.kernel.org > CC: linux-kernel@vger.kernel.org > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
On Thu, 27 Apr 2023 03:43:42 PDT (-0700), Conor Dooley wrote: > The dt-binding was defined before the extraction of csr access and > fence.i into their own extensions, and thus the presence of the I > base extension implies Zicsr and Zifencei. > There's no harm in adding them obviously, but for backwards > compatibility with DTs that existed prior to that extraction, software > is unable to differentiate between "i" and "i_zicsr_zifencei" without > any further information. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > CC: Conor Dooley <conor@kernel.org> > CC: Rob Herring <robh+dt@kernel.org> > CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> > CC: Paul Walmsley <paul.walmsley@sifive.com> > CC: Palmer Dabbelt <palmer@dabbelt.com> > CC: linux-riscv@lists.infradead.org > CC: devicetree@vger.kernel.org > CC: linux-kernel@vger.kernel.org > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 4c7ce4a37052..a93bc7eae928 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -85,6 +85,12 @@ properties: > User-Level ISA document, available from > https://riscv.org/specifications/ > > + Due to revisions of the ISA specification, some deviations > + have arisen over time. > + Notably, riscv,isa was defined prior to the creation of the > + Zicsr and Zifencei extensions and thus "i" implies > + "zicsr_zifencei". also Zihpm and Zicntr. I'm going to put this one on for-next, though. Thanks! > + > While the isa strings in ISA specification are case > insensitive, letters in the riscv,isa string must be all > lowercase to simplify parsing.
On Thu, 27 Apr 2023 11:43:42 +0100, Conor Dooley wrote: > The dt-binding was defined before the extraction of csr access and > fence.i into their own extensions, and thus the presence of the I > base extension implies Zicsr and Zifencei. > There's no harm in adding them obviously, but for backwards > compatibility with DTs that existed prior to that extraction, software > is unable to differentiate between "i" and "i_zicsr_zifencei" without > any further information. > > [...] Applied, thanks! [1/1] dt-bindings: riscv: explicitly mention assumption of Zicsr & Zifencei support https://git.kernel.org/palmer/c/41ebfc91f785 Best regards,
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 4c7ce4a37052..a93bc7eae928 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -85,6 +85,12 @@ properties: User-Level ISA document, available from https://riscv.org/specifications/ + Due to revisions of the ISA specification, some deviations + have arisen over time. + Notably, riscv,isa was defined prior to the creation of the + Zicsr and Zifencei extensions and thus "i" implies + "zicsr_zifencei". + While the isa strings in ISA specification are case insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing.
The dt-binding was defined before the extraction of csr access and fence.i into their own extensions, and thus the presence of the I base extension implies Zicsr and Zifencei. There's no harm in adding them obviously, but for backwards compatibility with DTs that existed prior to that extraction, software is unable to differentiate between "i" and "i_zicsr_zifencei" without any further information. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- CC: Conor Dooley <conor@kernel.org> CC: Rob Herring <robh+dt@kernel.org> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> CC: Paul Walmsley <paul.walmsley@sifive.com> CC: Palmer Dabbelt <palmer@dabbelt.com> CC: linux-riscv@lists.infradead.org CC: devicetree@vger.kernel.org CC: linux-kernel@vger.kernel.org --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+)