| Message ID | 20230504-oncoming-antihero-1ed69bb8f57d@spud (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Palmer Dabbelt |
| Headers | show |
| Series | ISA string parser cleanups++ | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes or riscv/for-next |
On Thu, May 04, 2023 at 07:14:26PM +0100, Conor Dooley wrote: > @@ -204,8 +204,10 @@ arch_initcall(riscv_cpuinfo_init); > * New entries to this struct should follow the ordering rules described above. > */ > static struct riscv_isa_ext_data isa_ext_arr[] = { > + __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), Heh, well that is not the right order, per the rules I wrote in the comment above. Whoops... > __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), > __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), > + __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), > __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
On Thu, May 04, 2023 at 07:14:26PM +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Zicsr/Zifencei were part of i when the port was written and are required > by the kernel. There's not much that userspace can do with this extra > information, but there is no harm in reporting an ISA string that closer > resembles the current versions of the ISA specifications either. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/include/asm/hwcap.h | 2 ++ > arch/riscv/kernel/cpu.c | 2 ++ > arch/riscv/kernel/cpufeature.c | 7 +++++++ > 3 files changed, 11 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 9af793970855..aa61031f7923 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -44,6 +44,8 @@ > #define RISCV_ISA_EXT_ZIHINTPAUSE 32 > #define RISCV_ISA_EXT_SVNAPOT 33 > #define RISCV_ISA_EXT_ZICBOZ 34 > +#define RISCV_ISA_EXT_ZICSR 35 > +#define RISCV_ISA_EXT_ZIFENCEI 36 > > #define RISCV_ISA_EXT_MAX 64 > #define RISCV_ISA_EXT_NAME_LEN_MAX 32 > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index b0c3ec0f2f5b..0d5d580dca61 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -204,8 +204,10 @@ arch_initcall(riscv_cpuinfo_init); > * New entries to this struct should follow the ordering rules described above. > */ > static struct riscv_isa_ext_data isa_ext_arr[] = { > + __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), > __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), > __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), > + __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), > __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index b425658bbf08..92f0e7b78eef 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -292,6 +292,13 @@ void __init riscv_fill_hwcap(void) > #undef SET_ISA_EXT_MAP > } > > + /* > + * Linux requires Zicsr & Zifencei, so we may as well always > + * set them. > + */ > + set_bit(RISCV_ISA_EXT_ZIFENCEI, this_isa); > + set_bit(RISCV_ISA_EXT_ZICSR, this_isa); > + > /* > * All "okay" hart should have same isa. Set HWCAP based on > * common capabilities of every "okay" hart, in case they don't > -- > 2.39.2 > Besides the ordering you pointed out, Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 9af793970855..aa61031f7923 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -44,6 +44,8 @@ #define RISCV_ISA_EXT_ZIHINTPAUSE 32 #define RISCV_ISA_EXT_SVNAPOT 33 #define RISCV_ISA_EXT_ZICBOZ 34 +#define RISCV_ISA_EXT_ZICSR 35 +#define RISCV_ISA_EXT_ZIFENCEI 36 #define RISCV_ISA_EXT_MAX 64 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index b0c3ec0f2f5b..0d5d580dca61 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -204,8 +204,10 @@ arch_initcall(riscv_cpuinfo_init); * New entries to this struct should follow the ordering rules described above. */ static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), + __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b425658bbf08..92f0e7b78eef 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -292,6 +292,13 @@ void __init riscv_fill_hwcap(void) #undef SET_ISA_EXT_MAP } + /* + * Linux requires Zicsr & Zifencei, so we may as well always + * set them. + */ + set_bit(RISCV_ISA_EXT_ZIFENCEI, this_isa); + set_bit(RISCV_ISA_EXT_ZICSR, this_isa); + /* * All "okay" hart should have same isa. Set HWCAP based on * common capabilities of every "okay" hart, in case they don't