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[v5,0/5] PCI: brcmstb: Configure appropriate HW CLKREQ# mode

Message ID 20230508220126.16241-1-jim2101024@gmail.com (mailing list archive)
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Series PCI: brcmstb: Configure appropriate HW CLKREQ# mode | expand

Message

Jim Quinlan May 8, 2023, 10:01 p.m. UTC
v5 -- Remove DT property "brcm,completion-timeout-us" from	 
      "DT bindings" commit.  Although this error may be reported	 
      as a completion timeout, its cause was traced to an	 
      internal bus timeout which may occur even when there is	 
      no PCIe access being processed.  We set a timeout of four	 
      seconds only if we are operating in "L1SS CLKREQ#" mode.
   -- Correct CEM 2.0 reference provided by HW engineer,
      s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
   -- Add newline to dev_info() string (Stefan)
   -- Change variable rval to unsigned (Stefan)
   -- s/implementaion/implementation/ (Bjorn)
   -- s/superpowersave/powersupersave/ (Bjorn)
   -- Slightly modify message on "PERST#" commit.
   -- Rebase to torvalds master

v4 -- New commit that asserts PERST# for 2711/RPi SOCs at PCIe RC
      driver probe() time.  This is done in Raspian Linux and its
      absence may be the cause of a failing test case.
   -- New commit that removes stale comment.

v3 -- Rewrote commit msgs and comments refering panics if L1SS
      is enabled/disabled; the code snippet that unadvertises L1SS
      eliminates the panic scenario. (Bjorn)
   -- Add reference for "400ns of CLKREQ# assertion" blurb (Bjorn)
   -- Put binding names in DT commit Subject (Bjorn)
   -- Add a verb to a commit's subject line (Bjorn)
   -- s/accomodat(\w+)/accommodat$1/g (Bjorn)
   -- Rewrote commit msgs and comments refering panics if L1SS
      is enabled/disabled; the code snippet that unadvertises L1SS
      eliminates the panic scenario. (Bjorn)

v2 -- Changed binding property 'brcm,completion-timeout-msec' to
      'brcm,completion-timeout-us'.  (StefanW for standard suffix).
   -- Warn when clamping timeout value, and include clamped
      region in message. Also add min and max in YAML. (StefanW)
   -- Qualify description of "brcm,completion-timeout-us" so that
      it refers to PCIe transactions. (StefanW)
   -- Remvove mention of Linux specifics in binding description. (StefanW)
   -- s/clkreq#/CLKREQ#/g (Bjorn)
   -- Refactor completion-timeout-us code to compare max and min to
      value given by the property (as opposed to the computed value).

v1 -- The current driver assumes the downstream devices can
      provide CLKREQ# for ASPM.  These commits accomodate devices
      w/ or w/o clkreq# and also handle L1SS-capable devices.

   -- The Raspian Linux folks have already been using a PCIe RC
      property "brcm,enable-l1ss".  These commits use the same
      property, in a backward-compatible manner, and the implementaion
      adds more detail and also automatically identifies devices w/o
      a clkreq# signal, i.e. most devices plugged into an RPi CM4
      IO board.

Jim Quinlan (5):
  dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property
  PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream
    device
  PCI: brcmstb: Set higher value for internal bus timeout
  PCI: brcmstb: Don't assume 2711 bootloader leaves PERST# asserted
  PCI: brcmstb: Remove stale comment

 .../bindings/pci/brcm,stb-pcie.yaml           |  9 ++
 drivers/pci/controller/pcie-brcmstb.c         | 91 ++++++++++++++++---
 2 files changed, 89 insertions(+), 11 deletions(-)


base-commit: ac9a78681b921877518763ba0e89202254349d1b

Comments

Cyril Brulebois May 9, 2023, 7:46 a.m. UTC | #1
Hi Jim,

Jim Quinlan <jim2101024@gmail.com> (2023-05-08):
> v5 -- Remove DT property "brcm,completion-timeout-us" from	 
>       "DT bindings" commit.  Although this error may be reported	 
>       as a completion timeout, its cause was traced to an	 
>       internal bus timeout which may occur even when there is	 
>       no PCIe access being processed.  We set a timeout of four	 
>       seconds only if we are operating in "L1SS CLKREQ#" mode.
>    -- Correct CEM 2.0 reference provided by HW engineer,
>       s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
>    -- Add newline to dev_info() string (Stefan)
>    -- Change variable rval to unsigned (Stefan)
>    -- s/implementaion/implementation/ (Bjorn)
>    -- s/superpowersave/powersupersave/ (Bjorn)
>    -- Slightly modify message on "PERST#" commit.
>    -- Rebase to torvalds master

Same results as with v4: looks good to me!

Using an official CM4 IO Board, I've successfully tested the same 9
setups as before, combining each:
 - CM4 Lite Rev 1.0
 - CM4 8/32 Rev 1.0
 - CM4 4/32 Rev 1.1

with each off-the-shelf PCIe/USB adapter at my disposal:
 - SupaHub PCE6U1C-R02, VER 006
 - SupaHub PCE6U1C-R02, VER 006S
 - Waveshare based on VIA VL805/806

Each system boots successfully, exposes the Kingston memory stick
plugged onto the PCIe/USB adapter, and happily reads data from it.

Note: I only tested each CM4 with the upgraded EEPROM (2023-01-11),
and without tweaking the DTB (i.e. without adding brcm,enable-l1ss).


Tested-By: Cyril Brulebois <cyril@debamax.com>


Cheers,
Jim Quinlan May 9, 2023, 11:22 a.m. UTC | #2
On Tue, May 9, 2023 at 3:47 AM Cyril Brulebois <kibi@debian.org> wrote:
>
> Hi Jim,
>
> Jim Quinlan <jim2101024@gmail.com> (2023-05-08):
> > v5 -- Remove DT property "brcm,completion-timeout-us" from
> >       "DT bindings" commit.  Although this error may be reported
> >       as a completion timeout, its cause was traced to an
> >       internal bus timeout which may occur even when there is
> >       no PCIe access being processed.  We set a timeout of four
> >       seconds only if we are operating in "L1SS CLKREQ#" mode.
> >    -- Correct CEM 2.0 reference provided by HW engineer,
> >       s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
> >    -- Add newline to dev_info() string (Stefan)
> >    -- Change variable rval to unsigned (Stefan)
> >    -- s/implementaion/implementation/ (Bjorn)
> >    -- s/superpowersave/powersupersave/ (Bjorn)
> >    -- Slightly modify message on "PERST#" commit.
> >    -- Rebase to torvalds master
>
> Same results as with v4: looks good to me!
>
> Using an official CM4 IO Board, I've successfully tested the same 9
> setups as before, combining each:
>  - CM4 Lite Rev 1.0
>  - CM4 8/32 Rev 1.0
>  - CM4 4/32 Rev 1.1
>
> with each off-the-shelf PCIe/USB adapter at my disposal:
>  - SupaHub PCE6U1C-R02, VER 006
>  - SupaHub PCE6U1C-R02, VER 006S
>  - Waveshare based on VIA VL805/806
>
> Each system boots successfully, exposes the Kingston memory stick
> plugged onto the PCIe/USB adapter, and happily reads data from it.
>
> Note: I only tested each CM4 with the upgraded EEPROM (2023-01-11),
> and without tweaking the DTB (i.e. without adding brcm,enable-l1ss).
>
>
> Tested-By: Cyril Brulebois <cyril@debamax.com>

Thanks a lot for doing this Cyril!
>
>
> Cheers,
> --
> Cyril Brulebois (kibi@debian.org)            <https://debamax.com/>
> D-I release manager -- Release team member -- Freelance Consultant