@@ -251,7 +251,7 @@ enum rtw89_band {
RTW89_BAND_2G = 0,
RTW89_BAND_5G = 1,
RTW89_BAND_6G = 2,
- RTW89_BAND_MAX,
+ RTW89_BAND_NUM,
};
enum rtw89_hw_rate {
@@ -434,27 +434,27 @@ enum rtw89_rate_section {
RTW89_RS_MCS, /* for HT/VHT/HE */
RTW89_RS_HEDCM,
RTW89_RS_OFFSET,
- RTW89_RS_MAX,
+ RTW89_RS_NUM,
RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
};
-enum rtw89_rate_max {
- RTW89_RATE_CCK_MAX = 4,
- RTW89_RATE_OFDM_MAX = 8,
- RTW89_RATE_MCS_MAX = 12,
- RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */
- RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */
+enum rtw89_rate_num {
+ RTW89_RATE_CCK_NUM = 4,
+ RTW89_RATE_OFDM_NUM = 8,
+ RTW89_RATE_MCS_NUM = 12,
+ RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */
+ RTW89_RATE_OFFSET_NUM = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */
};
enum rtw89_nss {
RTW89_NSS_1 = 0,
RTW89_NSS_2 = 1,
/* HE DCM only support 1ss and 2ss */
- RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1,
+ RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1,
RTW89_NSS_3 = 2,
RTW89_NSS_4 = 3,
- RTW89_NSS_MAX,
+ RTW89_NSS_NUM,
};
enum rtw89_ntx {
@@ -512,11 +512,11 @@ enum rtw89_fw_pkt_ofld_type {
};
struct rtw89_txpwr_byrate {
- s8 cck[RTW89_RATE_CCK_MAX];
- s8 ofdm[RTW89_RATE_OFDM_MAX];
- s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX];
- s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX];
- s8 offset[RTW89_RATE_OFFSET_MAX];
+ s8 cck[RTW89_RATE_CCK_NUM];
+ s8 ofdm[RTW89_RATE_OFDM_NUM];
+ s8 mcs[RTW89_NSS_NUM][RTW89_RATE_MCS_NUM];
+ s8 hedcm[RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
+ s8 offset[RTW89_RATE_OFFSET_NUM];
};
enum rtw89_bandwidth_section_num {
@@ -3815,7 +3815,7 @@ struct rtw89_power_trim_info {
struct rtw89_regd {
char alpha2[3];
- u8 txpwr_regd[RTW89_BAND_MAX];
+ u8 txpwr_regd[RTW89_BAND_NUM];
};
struct rtw89_regulatory_info {
@@ -4111,7 +4111,7 @@ struct rtw89_dev {
bool is_bt_iqk_timeout;
struct rtw89_fem_info fem;
- struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX];
+ struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM];
struct rtw89_tssi_info tssi;
struct rtw89_power_trim_info pwr_trim;
@@ -1494,19 +1494,19 @@ void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
}
EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl);
-static const u8 rtw89_rs_idx_max[] = {
- [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX,
- [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX,
- [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX,
- [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX,
- [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX,
+static const u8 rtw89_rs_idx_num[] = {
+ [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM,
+ [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM,
+ [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM,
+ [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_NUM,
+ [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM,
};
-static const u8 rtw89_rs_nss_max[] = {
+static const u8 rtw89_rs_nss_num[] = {
[RTW89_RS_CCK] = 1,
[RTW89_RS_OFDM] = 1,
- [RTW89_RS_MCS] = RTW89_NSS_MAX,
- [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX,
+ [RTW89_RS_MCS] = RTW89_NSS_NUM,
+ [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_NUM,
[RTW89_RS_OFFSET] = 1,
};
@@ -1519,9 +1519,9 @@ static const u8 _byr_of_rs[] = {
};
#define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs])
-#define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx))
+#define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_num[rs] + (idx))
#define _byr_chk(rs, nss, idx) \
- ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs])
+ ((nss) < rtw89_rs_nss_num[rs] && (idx) < rtw89_rs_idx_num[rs])
void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
const struct rtw89_txpwr_table *tbl)
@@ -2084,19 +2084,19 @@ void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
"[TXPWR] set txpwr byrate with ch=%d\n", ch);
- BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_CCK] % 4);
- BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_OFDM] % 4);
- BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_MCS] % 4);
- BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_HEDCM] % 4);
+ BUILD_BUG_ON(rtw89_rs_idx_num[RTW89_RS_CCK] % 4);
+ BUILD_BUG_ON(rtw89_rs_idx_num[RTW89_RS_OFDM] % 4);
+ BUILD_BUG_ON(rtw89_rs_idx_num[RTW89_RS_MCS] % 4);
+ BUILD_BUG_ON(rtw89_rs_idx_num[RTW89_RS_HEDCM] % 4);
addr = R_AX_PWR_BY_RATE;
for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) {
for (i = 0; i < ARRAY_SIZE(rs); i++) {
- if (cur.nss >= rtw89_rs_nss_max[rs[i]])
+ if (cur.nss >= rtw89_rs_nss_num[rs[i]])
continue;
cur.rs = rs[i];
- for (cur.idx = 0; cur.idx < rtw89_rs_idx_max[rs[i]];
+ for (cur.idx = 0; cur.idx < rtw89_rs_idx_num[rs[i]];
cur.idx++) {
v[cur.idx % 4] =
rtw89_phy_read_txpwr_byrate(rtwdev,
@@ -2129,15 +2129,15 @@ void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
.rs = RTW89_RS_OFFSET,
};
u8 band = chan->band_type;
- s8 v[RTW89_RATE_OFFSET_MAX] = {};
+ s8 v[RTW89_RATE_OFFSET_NUM] = {};
u32 val;
rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
- for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++)
+ for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM; desc.idx++)
v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc);
- BUILD_BUG_ON(RTW89_RATE_OFFSET_MAX != 5);
+ BUILD_BUG_ON(RTW89_RATE_OFFSET_NUM != 5);
val = FIELD_PREP(GENMASK(3, 0), v[0]) |
FIELD_PREP(GENMASK(7, 4), v[1]) |
FIELD_PREP(GENMASK(11, 8), v[2]) |
@@ -3305,7 +3305,7 @@ static const s8 _txpwr_track_delta_swingidx_2g_cck_a_p[] = {
0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4
};
-const u8 rtw89_8851b_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
+const u8 rtw89_8851b_tx_shape[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM]
[RTW89_REGD_NUM] = {
[0][0][RTW89_ACMA] = 0,
[0][0][RTW89_CN] = 0,
@@ -13,7 +13,7 @@ extern const struct rtw89_phy_table rtw89_8851b_phy_radioa_table;
extern const struct rtw89_phy_table rtw89_8851b_phy_nctl_table;
extern const struct rtw89_txpwr_table rtw89_8851b_byr_table;
extern const struct rtw89_txpwr_track_cfg rtw89_8851b_trk_cfg;
-extern const u8 rtw89_8851b_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
+extern const u8 rtw89_8851b_tx_shape[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM]
[RTW89_REGD_NUM];
extern const struct rtw89_rfe_parms rtw89_8851b_dflt_parms;
extern const struct rtw89_rfe_parms_conf rtw89_8851b_rfe_parms_conf[];
@@ -14666,7 +14666,7 @@ static const s8 _txpwr_track_delta_swingidx_2g_cck_a_p[] = {
0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
-const u8 rtw89_8852b_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
+const u8 rtw89_8852b_tx_shape[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM]
[RTW89_REGD_NUM] = {
[0][0][RTW89_ACMA] = 0,
[0][0][RTW89_CHILE] = 0,
@@ -14,7 +14,7 @@ extern const struct rtw89_phy_table rtw89_8852b_phy_radiob_table;
extern const struct rtw89_phy_table rtw89_8852b_phy_nctl_table;
extern const struct rtw89_txpwr_table rtw89_8852b_byr_table;
extern const struct rtw89_txpwr_track_cfg rtw89_8852b_trk_cfg;
-extern const u8 rtw89_8852b_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
+extern const u8 rtw89_8852b_tx_shape[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM]
[RTW89_REGD_NUM];
extern const struct rtw89_rfe_parms rtw89_8852b_dflt_parms;
@@ -31525,7 +31525,7 @@ static const s8 _txpwr_track_delta_swingidx_2g_cck_a_p[] = {
3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 5, 5, 5
};
-const u8 rtw89_8852c_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
+const u8 rtw89_8852c_tx_shape[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM]
[RTW89_REGD_NUM] = {
[0][0][RTW89_ACMA] = 0,
[0][0][RTW89_CHILE] = 0,
@@ -15,7 +15,7 @@ extern const struct rtw89_phy_table rtw89_8852c_phy_nctl_table;
extern const struct rtw89_txpwr_table rtw89_8852c_byr_table;
extern const struct rtw89_phy_tssi_dbw_table rtw89_8852c_tssi_dbw_table;
extern const struct rtw89_txpwr_track_cfg rtw89_8852c_trk_cfg;
-extern const u8 rtw89_8852c_tx_shape[RTW89_BAND_MAX][RTW89_RS_TX_SHAPE_NUM]
+extern const u8 rtw89_8852c_tx_shape[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM]
[RTW89_REGD_NUM];
extern const struct rtw89_rfe_parms rtw89_8852c_dflt_parms;