| Message ID | 20230623093445.3977772-2-quic_srichara@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | IPQ8074 pcie/wcss fixes | expand |
On Fri, Jun 23, 2023 at 03:04:42PM +0530, Sricharan Ramabadhran wrote: > PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074 > pcie slave addr size was initially set to 0x358, but > was wrongly changed to 0x168 as a part of > 'PCI: qcom: Sort and group registers and bitfield definitions' > Fixing it back to right value here. > > Without this pcie bring up on IPQ8074 is broken now. > > Fixes: 769e49d87b15 ("PCI: qcom: Sort and group registers and bitfield definitions") 769e49d87b15 appeared in v6.4-rc1, so ideally this would get merged before v6.4 releases on Monday. I can try to do that, given an ack from Manivannan. > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 4ab30892f6ef..59823beed13f 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -43,7 +43,7 @@ > #define PARF_PHY_REFCLK 0x4c > #define PARF_CONFIG_BITS 0x50 > #define PARF_DBI_BASE_ADDR 0x168 > -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ > +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x358 /* Register offset specific to IP ver 2.3.3 */ > #define PARF_MHI_CLOCK_RESET_CTRL 0x174 > #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 > #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 > -- > 2.34.1 >
On Fri, Jun 23, 2023 at 03:04:42PM +0530, Sricharan Ramabadhran wrote: > PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074 > pcie slave addr size was initially set to 0x358, but > was wrongly changed to 0x168 as a part of > 'PCI: qcom: Sort and group registers and bitfield definitions' > Fixing it back to right value here. 1) Make your subject line match the history. For example, you're fixing 769e49d87b15 ("PCI: qcom: Sort and group registers ..."), so your subject line should start with "PCI: qcom: ...". 2) It doesn't look like 769e49d87b15 changed PARF_SLV_ADDR_SPACE_SIZE_2_3_3: $ git show 769e49d87b15 | grep PARF_SLV_ADDR_SPACE_SIZE_2_3_3 +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16C /* Register offset specific to IP ver 2.3.3 */ -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16C /* Register offset specific to IP rev 2.3.3 */ What am I missing here? Do you have another out-of-tree patch that broke this? Bjorn > Without this pcie bring up on IPQ8074 is broken now. > > Fixes: 769e49d87b15 ("PCI: qcom: Sort and group registers and bitfield definitions") > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 4ab30892f6ef..59823beed13f 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -43,7 +43,7 @@ > #define PARF_PHY_REFCLK 0x4c > #define PARF_CONFIG_BITS 0x50 > #define PARF_DBI_BASE_ADDR 0x168 > -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ > +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x358 /* Register offset specific to IP ver 2.3.3 */ > #define PARF_MHI_CLOCK_RESET_CTRL 0x174 > #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 > #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 > -- > 2.34.1 >
On Fri, Jun 23, 2023 at 03:04:42PM +0530, Sricharan Ramabadhran wrote: > PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074 > pcie slave addr size was initially set to 0x358, but > was wrongly changed to 0x168 as a part of > 'PCI: qcom: Sort and group registers and bitfield definitions' > Fixing it back to right value here. > > Without this pcie bring up on IPQ8074 is broken now. > Subject prefix should be: "PCI: qcom: " > Fixes: 769e49d87b15 ("PCI: qcom: Sort and group registers and bitfield definitions") Fixes tag is referring to a wrong commit. Correct one is: 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions") > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 4ab30892f6ef..59823beed13f 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -43,7 +43,7 @@ > #define PARF_PHY_REFCLK 0x4c > #define PARF_CONFIG_BITS 0x50 > #define PARF_DBI_BASE_ADDR 0x168 > -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ > +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x358 /* Register offset specific to IP ver 2.3.3 */ You should just remove PARF_SLV_ADDR_SPACE_SIZE_2_3_3 and use PARF_SLV_ADDR_SPACE_SIZE which already has the value of 0x358. - Mani > #define PARF_MHI_CLOCK_RESET_CTRL 0x174 > #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 > #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 > -- > 2.34.1 >
Hi Bjorn, On 6/23/2023 11:30 PM, Bjorn Helgaas wrote: > On Fri, Jun 23, 2023 at 03:04:42PM +0530, Sricharan Ramabadhran wrote: >> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074 >> pcie slave addr size was initially set to 0x358, but >> was wrongly changed to 0x168 as a part of >> 'PCI: qcom: Sort and group registers and bitfield definitions' >> Fixing it back to right value here. > > 1) Make your subject line match the history. For example, you're > fixing 769e49d87b15 ("PCI: qcom: Sort and group registers ..."), so > your subject line should start with "PCI: qcom: ...". > ok, will fix. > 2) It doesn't look like 769e49d87b15 changed > PARF_SLV_ADDR_SPACE_SIZE_2_3_3: > > $ git show 769e49d87b15 | grep PARF_SLV_ADDR_SPACE_SIZE_2_3_3 > +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16C /* Register offset specific to IP ver 2.3.3 */ > -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16C /* Register offset specific to IP rev 2.3.3 */ > > What am I missing here? Do you have another out-of-tree patch that > broke this? 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions") broke it. Will change and post . Regards, Sricharan
On 6/24/2023 12:02 PM, Manivannan Sadhasivam wrote: > On Fri, Jun 23, 2023 at 03:04:42PM +0530, Sricharan Ramabadhran wrote: >> PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074 >> pcie slave addr size was initially set to 0x358, but >> was wrongly changed to 0x168 as a part of >> 'PCI: qcom: Sort and group registers and bitfield definitions' >> Fixing it back to right value here. >> >> Without this pcie bring up on IPQ8074 is broken now. >> > > Subject prefix should be: "PCI: qcom: " > >> Fixes: 769e49d87b15 ("PCI: qcom: Sort and group registers and bitfield definitions") > > Fixes tag is referring to a wrong commit. Correct one is: > 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions") > ok. >> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index 4ab30892f6ef..59823beed13f 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -43,7 +43,7 @@ >> #define PARF_PHY_REFCLK 0x4c >> #define PARF_CONFIG_BITS 0x50 >> #define PARF_DBI_BASE_ADDR 0x168 >> -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ >> +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x358 /* Register offset specific to IP ver 2.3.3 */ > > You should just remove PARF_SLV_ADDR_SPACE_SIZE_2_3_3 and use > PARF_SLV_ADDR_SPACE_SIZE which already has the value of 0x358. > ok Regards, Sricharan
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4ab30892f6ef..59823beed13f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -43,7 +43,7 @@ #define PARF_PHY_REFCLK 0x4c #define PARF_CONFIG_BITS 0x50 #define PARF_DBI_BASE_ADDR 0x168 -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x358 /* Register offset specific to IP ver 2.3.3 */ #define PARF_MHI_CLOCK_RESET_CTRL 0x174 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8
PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074 pcie slave addr size was initially set to 0x358, but was wrongly changed to 0x168 as a part of 'PCI: qcom: Sort and group registers and bitfield definitions' Fixing it back to right value here. Without this pcie bring up on IPQ8074 is broken now. Fixes: 769e49d87b15 ("PCI: qcom: Sort and group registers and bitfield definitions") Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> --- drivers/pci/controller/dwc/pcie-qcom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)