| Message ID | 36b5837e9e94465dd2b7d7a17bb84dea082f2ffa.1690364259.git.haibo1.xu@intel.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | RISCV: Add kvm Sstc timer selftest | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Series has a cover letter |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD 471aba2e4760 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 4 and now 4 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 9 this patch: 9 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 9 this patch: 9 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 23 lines checked |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Thu, Jul 27, 2023 at 03:20:07PM +0800, Haibo Xu wrote: > Add guest_get_vcpuid() helper to simplify accessing to per-cpu > private data. The sscratch CSR was used to store the vcpu id. > > Signed-off-by: Haibo Xu <haibo1.xu@intel.com> > --- > tools/testing/selftests/kvm/include/riscv/processor.h | 2 ++ > tools/testing/selftests/kvm/lib/riscv/processor.c | 8 ++++++++ > 2 files changed, 10 insertions(+) > > diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h > index 9ea6e7bedc61..ca53570ce6de 100644 > --- a/tools/testing/selftests/kvm/include/riscv/processor.h > +++ b/tools/testing/selftests/kvm/include/riscv/processor.h > @@ -165,4 +165,6 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, > unsigned long arg3, unsigned long arg4, > unsigned long arg5); > > +uint32_t guest_get_vcpuid(void); I'd also put this prototype somewhere common. > + > #endif /* SELFTEST_KVM_PROCESSOR_H */ > diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c > index f1b0be58a5dc..b8ad3e69a697 100644 > --- a/tools/testing/selftests/kvm/lib/riscv/processor.c > +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c > @@ -316,6 +316,9 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, > vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.sp), stack_vaddr + stack_size); > vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.pc), (unsigned long)guest_code); > > + /* Setup scratch regiter of guest */ typo: register The comment above is pretty useless since it just states what the code states, but with even less information, since it doesn't state how the sscratch register is getting set up. I'd either drop it or write it as /* Setup sscratch for guest_get_vcpuid() */ > + vcpu_set_reg(vcpu, RISCV_CSR_REG(sscratch), vcpu_id); > + > /* Setup default exception vector of guest */ > vcpu_set_reg(vcpu, RISCV_CSR_REG(stvec), (unsigned long)guest_unexp_trap); > > @@ -424,3 +427,8 @@ void vm_install_interrupt_handler(struct kvm_vm *vm, void (*handler)(struct ex_r > > handlers->exception_handlers[1][0] = handler; > } > + > +uint32_t guest_get_vcpuid(void) > +{ > + return csr_read(CSR_SSCRATCH); > +} > -- > 2.34.1 > Thanks, drew
On Fri, Jul 28, 2023 at 5:49 PM Andrew Jones <ajones@ventanamicro.com> wrote: > > On Thu, Jul 27, 2023 at 03:20:07PM +0800, Haibo Xu wrote: > > Add guest_get_vcpuid() helper to simplify accessing to per-cpu > > private data. The sscratch CSR was used to store the vcpu id. > > > > Signed-off-by: Haibo Xu <haibo1.xu@intel.com> > > --- > > tools/testing/selftests/kvm/include/riscv/processor.h | 2 ++ > > tools/testing/selftests/kvm/lib/riscv/processor.c | 8 ++++++++ > > 2 files changed, 10 insertions(+) > > > > diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h > > index 9ea6e7bedc61..ca53570ce6de 100644 > > --- a/tools/testing/selftests/kvm/include/riscv/processor.h > > +++ b/tools/testing/selftests/kvm/include/riscv/processor.h > > @@ -165,4 +165,6 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, > > unsigned long arg3, unsigned long arg4, > > unsigned long arg5); > > > > +uint32_t guest_get_vcpuid(void); > > I'd also put this prototype somewhere common. > > > + > > #endif /* SELFTEST_KVM_PROCESSOR_H */ > > diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c > > index f1b0be58a5dc..b8ad3e69a697 100644 > > --- a/tools/testing/selftests/kvm/lib/riscv/processor.c > > +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c > > @@ -316,6 +316,9 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, > > vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.sp), stack_vaddr + stack_size); > > vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.pc), (unsigned long)guest_code); > > > > + /* Setup scratch regiter of guest */ > > typo: register > > The comment above is pretty useless since it just states what the code > states, but with even less information, since it doesn't state how the > sscratch register is getting set up. I'd either drop it or write it > as > > /* Setup sscratch for guest_get_vcpuid() */ > > > + vcpu_set_reg(vcpu, RISCV_CSR_REG(sscratch), vcpu_id); > > + > > /* Setup default exception vector of guest */ > > vcpu_set_reg(vcpu, RISCV_CSR_REG(stvec), (unsigned long)guest_unexp_trap); > > > > @@ -424,3 +427,8 @@ void vm_install_interrupt_handler(struct kvm_vm *vm, void (*handler)(struct ex_r > > > > handlers->exception_handlers[1][0] = handler; > > } > > + > > +uint32_t guest_get_vcpuid(void) > > +{ > > + return csr_read(CSR_SSCRATCH); > > +} > > -- > > 2.34.1 > > > Sure! will fix them in v2. Thanks, Haibo > Thanks, > drew
diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h index 9ea6e7bedc61..ca53570ce6de 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -165,4 +165,6 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, unsigned long arg3, unsigned long arg4, unsigned long arg5); +uint32_t guest_get_vcpuid(void); + #endif /* SELFTEST_KVM_PROCESSOR_H */ diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c index f1b0be58a5dc..b8ad3e69a697 100644 --- a/tools/testing/selftests/kvm/lib/riscv/processor.c +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c @@ -316,6 +316,9 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id, vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.sp), stack_vaddr + stack_size); vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.pc), (unsigned long)guest_code); + /* Setup scratch regiter of guest */ + vcpu_set_reg(vcpu, RISCV_CSR_REG(sscratch), vcpu_id); + /* Setup default exception vector of guest */ vcpu_set_reg(vcpu, RISCV_CSR_REG(stvec), (unsigned long)guest_unexp_trap); @@ -424,3 +427,8 @@ void vm_install_interrupt_handler(struct kvm_vm *vm, void (*handler)(struct ex_r handlers->exception_handlers[1][0] = handler; } + +uint32_t guest_get_vcpuid(void) +{ + return csr_read(CSR_SSCRATCH); +}
Add guest_get_vcpuid() helper to simplify accessing to per-cpu private data. The sscratch CSR was used to store the vcpu id. Signed-off-by: Haibo Xu <haibo1.xu@intel.com> --- tools/testing/selftests/kvm/include/riscv/processor.h | 2 ++ tools/testing/selftests/kvm/lib/riscv/processor.c | 8 ++++++++ 2 files changed, 10 insertions(+)