| Message ID | 20230823231059.3363698-4-pulehui@huaweicloud.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support cpu v4 insns for RV64 | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/tree_selection | fail | Failed to apply to next/pending-fixes, riscv/for-next or riscv/master |
Pu Lehui <pulehui@huaweicloud.com> writes: > From: Pu Lehui <pulehui@huawei.com> > > Add support sign-extension mov instructions for RV64. > > Signed-off-by: Pu Lehui <pulehui@huawei.com> > --- > arch/riscv/net/bpf_jit_comp64.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c > index fd36cb17101a..d1497182cacf 100644 > --- a/arch/riscv/net/bpf_jit_comp64.c > +++ b/arch/riscv/net/bpf_jit_comp64.c > @@ -1047,7 +1047,19 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, > emit_zext_32(rd, ctx); > break; > } > - emit_mv(rd, rs, ctx); > + switch (insn->off) { > + case 0: > + emit_mv(rd, rs, ctx); > + break; > + case 8: > + case 16: > + emit_slli(rs, rs, 64 - insn->off, ctx); > + emit_srai(rd, rs, 64 - insn->off, ctx); You're clobbering the source register (rs) here, which is correct. (Side note: Maybe it's time to add Zbb support to the JIT soon! ;-)) Björn
Björn Töpel <bjorn@kernel.org> writes: > Pu Lehui <pulehui@huaweicloud.com> writes: > >> From: Pu Lehui <pulehui@huawei.com> >> >> Add support sign-extension mov instructions for RV64. >> >> Signed-off-by: Pu Lehui <pulehui@huawei.com> >> --- >> arch/riscv/net/bpf_jit_comp64.c | 14 +++++++++++++- >> 1 file changed, 13 insertions(+), 1 deletion(-) >> >> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c >> index fd36cb17101a..d1497182cacf 100644 >> --- a/arch/riscv/net/bpf_jit_comp64.c >> +++ b/arch/riscv/net/bpf_jit_comp64.c >> @@ -1047,7 +1047,19 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, >> emit_zext_32(rd, ctx); >> break; >> } >> - emit_mv(rd, rs, ctx); >> + switch (insn->off) { >> + case 0: >> + emit_mv(rd, rs, ctx); >> + break; >> + case 8: >> + case 16: >> + emit_slli(rs, rs, 64 - insn->off, ctx); >> + emit_srai(rd, rs, 64 - insn->off, ctx); > > You're clobbering the source register (rs) here, which is correct. Too quick! s/correct/incorrect/! :-)
On 2023/8/24 2:14, Björn Töpel wrote: > Pu Lehui <pulehui@huaweicloud.com> writes: > >> From: Pu Lehui <pulehui@huawei.com> >> >> Add support sign-extension mov instructions for RV64. >> >> Signed-off-by: Pu Lehui <pulehui@huawei.com> >> --- >> arch/riscv/net/bpf_jit_comp64.c | 14 +++++++++++++- >> 1 file changed, 13 insertions(+), 1 deletion(-) >> >> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c >> index fd36cb17101a..d1497182cacf 100644 >> --- a/arch/riscv/net/bpf_jit_comp64.c >> +++ b/arch/riscv/net/bpf_jit_comp64.c >> @@ -1047,7 +1047,19 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, >> emit_zext_32(rd, ctx); >> break; >> } >> - emit_mv(rd, rs, ctx); >> + switch (insn->off) { >> + case 0: >> + emit_mv(rd, rs, ctx); >> + break; >> + case 8: >> + case 16: >> + emit_slli(rs, rs, 64 - insn->off, ctx); >> + emit_srai(rd, rs, 64 - insn->off, ctx); > > You're clobbering the source register (rs) here, which is correct. alright, will fix it > > (Side note: Maybe it's time to add Zbb support to the JIT soon! ;-)) > > > Björn
diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c index fd36cb17101a..d1497182cacf 100644 --- a/arch/riscv/net/bpf_jit_comp64.c +++ b/arch/riscv/net/bpf_jit_comp64.c @@ -1047,7 +1047,19 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, emit_zext_32(rd, ctx); break; } - emit_mv(rd, rs, ctx); + switch (insn->off) { + case 0: + emit_mv(rd, rs, ctx); + break; + case 8: + case 16: + emit_slli(rs, rs, 64 - insn->off, ctx); + emit_srai(rd, rs, 64 - insn->off, ctx); + break; + case 32: + emit_addiw(rd, rs, 0, ctx); + break; + } if (!is64 && !aux->verifier_zext) emit_zext_32(rd, ctx); break;