diff mbox series

[2/2] drivers/drm/i915: Honor limits->max_bpp while computing DSC max input bpp

Message ID 20230823115425.715644-3-ankit.k.nautiyal@intel.com (mailing list archive)
State New, archived
Headers show
Series eDP DSC fixes | expand

Commit Message

Nautiyal, Ankit K Aug. 23, 2023, 11:54 a.m. UTC
Edid specific BPC constraints are stored in limits->max_bpp. Honor these
limits while computing the input bpp for DSC.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Stanislav Lisovskiy Aug. 24, 2023, 9:29 a.m. UTC | #1
On Wed, Aug 23, 2023 at 05:24:25PM +0530, Ankit Nautiyal wrote:
> Edid specific BPC constraints are stored in limits->max_bpp. Honor these
> limits while computing the input bpp for DSC.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

That is kind of funny, I can see this patch in my mails but can't
see the other one you had "Default 8 bpc support when DSC is supported",
which is visible from patchwork.
Anyways I give r-b for that one as well.

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5b48bfe09d0e..2a7f6cfe2832 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2061,9 +2061,11 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  	if (forced_bpp) {
>  		pipe_bpp = forced_bpp;
>  	} else {
> +		u8 max_bpc = limits->max_bpp / 3;
> +
>  		/* For eDP use max bpp that can be supported with DSC. */
>  		pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
> -							conn_state->max_requested_bpc);
> +							min(max_bpc, conn_state->max_requested_bpc));
>  		if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
>  			drm_dbg_kms(&i915->drm,
>  				    "Computed BPC is not in DSC BPC limits\n");
> -- 
> 2.40.1
>
Jani Nikula Aug. 24, 2023, 9:44 a.m. UTC | #2
On Wed, 23 Aug 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> Edid specific BPC constraints are stored in limits->max_bpp. Honor these
> limits while computing the input bpp for DSC.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5b48bfe09d0e..2a7f6cfe2832 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2061,9 +2061,11 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>  	if (forced_bpp) {
>  		pipe_bpp = forced_bpp;
>  	} else {
> +		u8 max_bpc = limits->max_bpp / 3;
> +

		int max_bpc = min_t(int, limits->max_bpp / 3, conn_state->max_requested_bpc);

>  		/* For eDP use max bpp that can be supported with DSC. */
>  		pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, max_bbc);

Nitpick, IMO looks cleaner this way, as well as uses int instead of u8
for computations.

BR,
Jani.

>  		if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
>  			drm_dbg_kms(&i915->drm,
>  				    "Computed BPC is not in DSC BPC limits\n");
Nautiyal, Ankit K Aug. 24, 2023, 11:34 a.m. UTC | #3
Thanks Stan for the review.

Regards,

Ankit

On 8/24/2023 2:59 PM, Lisovskiy, Stanislav wrote:
> On Wed, Aug 23, 2023 at 05:24:25PM +0530, Ankit Nautiyal wrote:
>> Edid specific BPC constraints are stored in limits->max_bpp. Honor these
>> limits while computing the input bpp for DSC.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
>
> That is kind of funny, I can see this patch in my mails but can't
> see the other one you had "Default 8 bpc support when DSC is supported",
> which is visible from patchwork.
> Anyways I give r-b for that one as well.
>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
>>   1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 5b48bfe09d0e..2a7f6cfe2832 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -2061,9 +2061,11 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>>   	if (forced_bpp) {
>>   		pipe_bpp = forced_bpp;
>>   	} else {
>> +		u8 max_bpc = limits->max_bpp / 3;
>> +
>>   		/* For eDP use max bpp that can be supported with DSC. */
>>   		pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
>> -							conn_state->max_requested_bpc);
>> +							min(max_bpc, conn_state->max_requested_bpc));
>>   		if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
>>   			drm_dbg_kms(&i915->drm,
>>   				    "Computed BPC is not in DSC BPC limits\n");
>> -- 
>> 2.40.1
>>
Nautiyal, Ankit K Aug. 24, 2023, 11:37 a.m. UTC | #4
On 8/24/2023 3:14 PM, Jani Nikula wrote:
> On Wed, 23 Aug 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> Edid specific BPC constraints are stored in limits->max_bpp. Honor these
>> limits while computing the input bpp for DSC.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 4 +++-
>>   1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 5b48bfe09d0e..2a7f6cfe2832 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -2061,9 +2061,11 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
>>   	if (forced_bpp) {
>>   		pipe_bpp = forced_bpp;
>>   	} else {
>> +		u8 max_bpc = limits->max_bpp / 3;
>> +
> 		int max_bpc = min_t(int, limits->max_bpp / 3, conn_state->max_requested_bpc);
>
>>   		/* For eDP use max bpp that can be supported with DSC. */
>>   		pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, max_bbc);
> Nitpick, IMO looks cleaner this way, as well as uses int instead of u8
> for computations.
>
> BR,
> Jani.

Thanks Jani for the comments, it does makes sense. Will fix in next 
version shortly.

Regards,

Ankit

>>   		if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
>>   			drm_dbg_kms(&i915->drm,
>>   				    "Computed BPC is not in DSC BPC limits\n");
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5b48bfe09d0e..2a7f6cfe2832 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2061,9 +2061,11 @@  static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 	if (forced_bpp) {
 		pipe_bpp = forced_bpp;
 	} else {
+		u8 max_bpc = limits->max_bpp / 3;
+
 		/* For eDP use max bpp that can be supported with DSC. */
 		pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
-							conn_state->max_requested_bpc);
+							min(max_bpc, conn_state->max_requested_bpc));
 		if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
 			drm_dbg_kms(&i915->drm,
 				    "Computed BPC is not in DSC BPC limits\n");