| Message ID | 20230912115728.172982-1-bjorn@kernel.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | RISC-V BLAKE2s Vector implementation | expand |
On Tue, Sep 12, 2023 at 01:57:22PM +0200, Björn Töpel wrote: > From: Björn Töpel <bjorn@rivosinc.com> > > Hi, > > This is Andy's kernel mode vector V2 series [1], with my BLAKE2s > AVX-512-to-RISC-V translation patch appended. > > I've tagged it as RFC, since Andy's series is still not in-tree yet. > > It's a first step towards a Vector aided Wireguard! ;-) This has the same problems as Andy's stuff & doesn't build properly for the automation. What is the plan between yourself and Andy for submitting a version of the in-kernel vector support that passes build testing? Cheers, Conor. > > > Cheers, > Björn > > [1] https://lore.kernel.org/linux-riscv/20230721112855.1006-1-andy.chiu@sifive.com/ > > Andy Chiu (3): > riscv: sched: defer restoring Vector context for user > riscv: vector: do not pass task_struct into > riscv_v_vstate_{save,restore}() > riscv: vector: allow kernel-mode Vector with preemption > > Björn Töpel (1): > riscv: Add BLAKE2s V implementation > > Greentime Hu (2): > riscv: Add support for kernel mode vector > riscv: Add vector extension XOR implementation > > arch/riscv/Kbuild | 2 +- > arch/riscv/Kconfig | 10 ++ > arch/riscv/crypto/Kconfig | 16 +++ > arch/riscv/crypto/Makefile | 6 + > arch/riscv/crypto/blake2s-glue.c | 39 ++++++ > arch/riscv/crypto/blake2s-v.S | 164 +++++++++++++++++++++++++ > arch/riscv/include/asm/entry-common.h | 13 ++ > arch/riscv/include/asm/processor.h | 2 + > arch/riscv/include/asm/simd.h | 52 ++++++++ > arch/riscv/include/asm/thread_info.h | 6 + > arch/riscv/include/asm/vector.h | 50 ++++++-- > arch/riscv/include/asm/xor.h | 82 +++++++++++++ > arch/riscv/kernel/Makefile | 1 + > arch/riscv/kernel/asm-offsets.c | 2 + > arch/riscv/kernel/entry.S | 45 +++++++ > arch/riscv/kernel/kernel_mode_vector.c | 146 ++++++++++++++++++++++ > arch/riscv/kernel/process.c | 10 +- > arch/riscv/kernel/ptrace.c | 2 +- > arch/riscv/kernel/signal.c | 4 +- > arch/riscv/kernel/vector.c | 5 +- > arch/riscv/lib/Makefile | 1 + > arch/riscv/lib/xor.S | 81 ++++++++++++ > crypto/Kconfig | 3 + > drivers/net/Kconfig | 1 + > 24 files changed, 725 insertions(+), 18 deletions(-) > create mode 100644 arch/riscv/crypto/Kconfig > create mode 100644 arch/riscv/crypto/Makefile > create mode 100644 arch/riscv/crypto/blake2s-glue.c > create mode 100644 arch/riscv/crypto/blake2s-v.S > create mode 100644 arch/riscv/include/asm/simd.h > create mode 100644 arch/riscv/include/asm/xor.h > create mode 100644 arch/riscv/kernel/kernel_mode_vector.c > create mode 100644 arch/riscv/lib/xor.S > > > base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d > -- > 2.39.2 >
Conor Dooley <conor.dooley@microchip.com> writes: > On Tue, Sep 12, 2023 at 01:57:22PM +0200, Björn Töpel wrote: >> From: Björn Töpel <bjorn@rivosinc.com> >> >> Hi, >> >> This is Andy's kernel mode vector V2 series [1], with my BLAKE2s >> AVX-512-to-RISC-V translation patch appended. >> >> I've tagged it as RFC, since Andy's series is still not in-tree yet. >> >> It's a first step towards a Vector aided Wireguard! ;-) > > This has the same problems as Andy's stuff & doesn't build properly for the > automation. What is the plan between yourself and Andy for submitting a > version of the in-kernel vector support that passes build testing? I'll synch up with Andy! I'm not even sure the blake2s patch should part of the "in-kernel vector" series at all. Thanks, Björn
On Thu, Sep 14, 2023 at 02:59:30PM +0200, Björn Töpel wrote: > Conor Dooley <conor.dooley@microchip.com> writes: > > > On Tue, Sep 12, 2023 at 01:57:22PM +0200, Björn Töpel wrote: > >> From: Björn Töpel <bjorn@rivosinc.com> > >> > >> Hi, > >> > >> This is Andy's kernel mode vector V2 series [1], with my BLAKE2s > >> AVX-512-to-RISC-V translation patch appended. > >> > >> I've tagged it as RFC, since Andy's series is still not in-tree yet. > >> > >> It's a first step towards a Vector aided Wireguard! ;-) > > > > This has the same problems as Andy's stuff & doesn't build properly for the > > automation. What is the plan between yourself and Andy for submitting a > > version of the in-kernel vector support that passes build testing? > > I'll synch up with Andy! I'm not even sure the blake2s patch should part > of the "in-kernel vector" series at all. The in-kernel vector stuff should come with a user, otherwise it's dead code :)
Conor Dooley <conor.dooley@microchip.com> writes: > On Thu, Sep 14, 2023 at 02:59:30PM +0200, Björn Töpel wrote: >> Conor Dooley <conor.dooley@microchip.com> writes: >> >> > On Tue, Sep 12, 2023 at 01:57:22PM +0200, Björn Töpel wrote: >> >> From: Björn Töpel <bjorn@rivosinc.com> >> >> >> >> Hi, >> >> >> >> This is Andy's kernel mode vector V2 series [1], with my BLAKE2s >> >> AVX-512-to-RISC-V translation patch appended. >> >> >> >> I've tagged it as RFC, since Andy's series is still not in-tree yet. >> >> >> >> It's a first step towards a Vector aided Wireguard! ;-) >> > >> > This has the same problems as Andy's stuff & doesn't build properly for the >> > automation. What is the plan between yourself and Andy for submitting a >> > version of the in-kernel vector support that passes build testing? >> >> I'll synch up with Andy! I'm not even sure the blake2s patch should part >> of the "in-kernel vector" series at all. > > The in-kernel vector stuff should come with a user, otherwise it's dead > code :) Sure, just so we're on the same page; Patch 3 (Vector XOR) is a user from my perspective, no?
On Thu, Sep 14, 2023 at 04:15:10PM +0200, Björn Töpel wrote: > Conor Dooley <conor.dooley@microchip.com> writes: > > > On Thu, Sep 14, 2023 at 02:59:30PM +0200, Björn Töpel wrote: > >> Conor Dooley <conor.dooley@microchip.com> writes: > >> > >> > On Tue, Sep 12, 2023 at 01:57:22PM +0200, Björn Töpel wrote: > >> >> From: Björn Töpel <bjorn@rivosinc.com> > >> >> > >> >> Hi, > >> >> > >> >> This is Andy's kernel mode vector V2 series [1], with my BLAKE2s > >> >> AVX-512-to-RISC-V translation patch appended. > >> >> > >> >> I've tagged it as RFC, since Andy's series is still not in-tree yet. > >> >> > >> >> It's a first step towards a Vector aided Wireguard! ;-) > >> > > >> > This has the same problems as Andy's stuff & doesn't build properly for the > >> > automation. What is the plan between yourself and Andy for submitting a > >> > version of the in-kernel vector support that passes build testing? > >> > >> I'll synch up with Andy! I'm not even sure the blake2s patch should part > >> of the "in-kernel vector" series at all. > > > > The in-kernel vector stuff should come with a user, otherwise it's dead > > code :) > > Sure, just so we're on the same page; Patch 3 (Vector XOR) is a user > from my perspective, no? D'oh
On Thu, Sep 14, 2023 at 10:18 PM Conor Dooley <conor@kernel.org> wrote: > > On Thu, Sep 14, 2023 at 04:15:10PM +0200, Björn Töpel wrote: > > Conor Dooley <conor.dooley@microchip.com> writes: > > > > > On Thu, Sep 14, 2023 at 02:59:30PM +0200, Björn Töpel wrote: > > >> Conor Dooley <conor.dooley@microchip.com> writes: > > >> > > >> > On Tue, Sep 12, 2023 at 01:57:22PM +0200, Björn Töpel wrote: > > >> >> From: Björn Töpel <bjorn@rivosinc.com> > > >> >> > > >> >> Hi, > > >> >> > > >> >> This is Andy's kernel mode vector V2 series [1], with my BLAKE2s > > >> >> AVX-512-to-RISC-V translation patch appended. > > >> >> > > >> >> I've tagged it as RFC, since Andy's series is still not in-tree yet. > > >> >> > > >> >> It's a first step towards a Vector aided Wireguard! ;-) > > >> > > > >> > This has the same problems as Andy's stuff & doesn't build properly for the > > >> > automation. What is the plan between yourself and Andy for submitting a > > >> > version of the in-kernel vector support that passes build testing? > > >> > > >> I'll synch up with Andy! I'm not even sure the blake2s patch should part > > >> of the "in-kernel vector" series at all. Hi, yes, I have a plan to fix it recently. Please expect a respin of the kernel-mode vector in 1~2 weeks, if this doesn't seem too long to you. > > > > > > The in-kernel vector stuff should come with a user, otherwise it's dead > > > code :) > > > > Sure, just so we're on the same page; Patch 3 (Vector XOR) is a user > > from my perspective, no? > > D'oh Thanks, Andy
From: Björn Töpel <bjorn@rivosinc.com> Hi, This is Andy's kernel mode vector V2 series [1], with my BLAKE2s AVX-512-to-RISC-V translation patch appended. I've tagged it as RFC, since Andy's series is still not in-tree yet. It's a first step towards a Vector aided Wireguard! ;-) Cheers, Björn [1] https://lore.kernel.org/linux-riscv/20230721112855.1006-1-andy.chiu@sifive.com/ Andy Chiu (3): riscv: sched: defer restoring Vector context for user riscv: vector: do not pass task_struct into riscv_v_vstate_{save,restore}() riscv: vector: allow kernel-mode Vector with preemption Björn Töpel (1): riscv: Add BLAKE2s V implementation Greentime Hu (2): riscv: Add support for kernel mode vector riscv: Add vector extension XOR implementation arch/riscv/Kbuild | 2 +- arch/riscv/Kconfig | 10 ++ arch/riscv/crypto/Kconfig | 16 +++ arch/riscv/crypto/Makefile | 6 + arch/riscv/crypto/blake2s-glue.c | 39 ++++++ arch/riscv/crypto/blake2s-v.S | 164 +++++++++++++++++++++++++ arch/riscv/include/asm/entry-common.h | 13 ++ arch/riscv/include/asm/processor.h | 2 + arch/riscv/include/asm/simd.h | 52 ++++++++ arch/riscv/include/asm/thread_info.h | 6 + arch/riscv/include/asm/vector.h | 50 ++++++-- arch/riscv/include/asm/xor.h | 82 +++++++++++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/asm-offsets.c | 2 + arch/riscv/kernel/entry.S | 45 +++++++ arch/riscv/kernel/kernel_mode_vector.c | 146 ++++++++++++++++++++++ arch/riscv/kernel/process.c | 10 +- arch/riscv/kernel/ptrace.c | 2 +- arch/riscv/kernel/signal.c | 4 +- arch/riscv/kernel/vector.c | 5 +- arch/riscv/lib/Makefile | 1 + arch/riscv/lib/xor.S | 81 ++++++++++++ crypto/Kconfig | 3 + drivers/net/Kconfig | 1 + 24 files changed, 725 insertions(+), 18 deletions(-) create mode 100644 arch/riscv/crypto/Kconfig create mode 100644 arch/riscv/crypto/Makefile create mode 100644 arch/riscv/crypto/blake2s-glue.c create mode 100644 arch/riscv/crypto/blake2s-v.S create mode 100644 arch/riscv/include/asm/simd.h create mode 100644 arch/riscv/include/asm/xor.h create mode 100644 arch/riscv/kernel/kernel_mode_vector.c create mode 100644 arch/riscv/lib/xor.S base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d