| Message ID | 20230915-aloe-dollar-994937477776@spud (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | d3eabf2f2c81f8b0de0b75c6f41b875c501eb33b |
| Headers | show |
| Series | [v1] RISC-V: capitalise CMO op macros | expand |
On Fri, Sep 15, 2023 at 04:40:44PM +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The CMO op macros initially used lower case, as the original iteration > of the ALT_CMO_OP alternative stringified the first parameter to > finalise the assembly for the standard variant. > As a knock-on, the T-Head versions of these CMOs had to use mixed case > defines. Commit dd23e9535889 ("RISC-V: replace cbom instructions with > an insn-def") removed the asm construction with stringify, replacing it > an insn-def macro, rending the lower-case surplus to requirements. > As far as I can tell from a brief check, CBO_zero does not see similar > use and didn't require the mixed case define in the first place. > Replace the lower case characters now for consistency with other > insn-def macros in the standard and T-Head forms, and adjust the > callsites. > > Suggested-by: Andrew Jones <ajones@ventanamicro.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > CC: Paul Walmsley <paul.walmsley@sifive.com> > CC: Palmer Dabbelt <palmer@dabbelt.com> > CC: linux-riscv@lists.infradead.org > CC: linux-kernel@vger.kernel.org > --- > arch/riscv/include/asm/errata_list.h | 6 +++--- > arch/riscv/include/asm/insn-def.h | 8 +++---- > arch/riscv/lib/clear_page.S | 32 ++++++++++++++-------------- > arch/riscv/mm/dma-noncoherent.c | 8 +++---- > arch/riscv/mm/pmem.c | 4 ++-- > 5 files changed, 29 insertions(+), 29 deletions(-) > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h > index e2ecd01bfac7..5801af83d154 100644 > --- a/arch/riscv/include/asm/errata_list.h > +++ b/arch/riscv/include/asm/errata_list.h > @@ -117,9 +117,9 @@ asm volatile(ALTERNATIVE( \ > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > * 0000000 11001 00000 000 00000 0001011 > */ > -#define THEAD_inval_A0 ".long 0x0265000b" > -#define THEAD_clean_A0 ".long 0x0245000b" > -#define THEAD_flush_A0 ".long 0x0275000b" > +#define THEAD_INVAL_A0 ".long 0x0265000b" > +#define THEAD_CLEAN_A0 ".long 0x0245000b" > +#define THEAD_FLUSH_A0 ".long 0x0275000b" > #define THEAD_SYNC_S ".long 0x0190000b" > > #define ALT_CMO_OP(_op, _start, _size, _cachesize) \ > diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h > index 6960beb75f32..e27179b26086 100644 > --- a/arch/riscv/include/asm/insn-def.h > +++ b/arch/riscv/include/asm/insn-def.h > @@ -180,19 +180,19 @@ > INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(51), \ > __RD(0), RS1(gaddr), RS2(vmid)) > > -#define CBO_inval(base) \ > +#define CBO_INVAL(base) \ > INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ > RS1(base), SIMM12(0)) > > -#define CBO_clean(base) \ > +#define CBO_CLEAN(base) \ > INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ > RS1(base), SIMM12(1)) > > -#define CBO_flush(base) \ > +#define CBO_FLUSH(base) \ > INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ > RS1(base), SIMM12(2)) > > -#define CBO_zero(base) \ > +#define CBO_ZERO(base) \ > INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ > RS1(base), SIMM12(4)) > > diff --git a/arch/riscv/lib/clear_page.S b/arch/riscv/lib/clear_page.S > index d7a256eb53f4..b22de1231144 100644 > --- a/arch/riscv/lib/clear_page.S > +++ b/arch/riscv/lib/clear_page.S > @@ -29,41 +29,41 @@ SYM_FUNC_START(clear_page) > lw a1, riscv_cboz_block_size > add a2, a0, a2 > .Lzero_loop: > - CBO_zero(a0) > + CBO_ZERO(a0) > add a0, a0, a1 > CBOZ_ALT(11, "bltu a0, a2, .Lzero_loop; ret", "nop; nop") > - CBO_zero(a0) > + CBO_ZERO(a0) > add a0, a0, a1 > CBOZ_ALT(10, "bltu a0, a2, .Lzero_loop; ret", "nop; nop") > - CBO_zero(a0) > + CBO_ZERO(a0) > add a0, a0, a1 > - CBO_zero(a0) > + CBO_ZERO(a0) > add a0, a0, a1 > CBOZ_ALT(9, "bltu a0, a2, .Lzero_loop; ret", "nop; nop") > - CBO_zero(a0) > + CBO_ZERO(a0) > add a0, a0, a1 > - CBO_zero(a0) > + CBO_ZERO(a0) > add a0, a0, a1 > - CBO_zero(a0) > + CBO_ZERO(a0) > add a0, a0, a1 > - CBO_zero(a0) > + CBO_ZERO(a0) > add a0, a0, a1 > CBOZ_ALT(8, "bltu a0, a2, .Lzero_loop; ret", "nop; nop") > - CBO_zero(a0) > + CBO_ZERO(a0) > add a0, a0, a1 > - CBO_zero(a0) > + CBO_ZERO(a0) > add a0, a0, a1 > - CBO_zero(a0) > + CBO_ZERO(a0) > add a0, a0, a1 > - CBO_zero(a0) > + CBO_ZERO(a0) > add a0, a0, a1 > - CBO_zero(a0) > + CBO_ZERO(a0) > add a0, a0, a1 > - CBO_zero(a0) > + CBO_ZERO(a0) > add a0, a0, a1 > - CBO_zero(a0) > + CBO_ZERO(a0) > add a0, a0, a1 > - CBO_zero(a0) > + CBO_ZERO(a0) > add a0, a0, a1 > bltu a0, a2, .Lzero_loop > ret > diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c > index b76e7e192eb1..607d5f47d437 100644 > --- a/arch/riscv/mm/dma-noncoherent.c > +++ b/arch/riscv/mm/dma-noncoherent.c > @@ -31,7 +31,7 @@ static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size) > return; > } > #endif > - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); > + ALT_CMO_OP(CLEAN, vaddr, size, riscv_cbom_block_size); > } > > static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size) > @@ -45,7 +45,7 @@ static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size) > } > #endif > > - ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size); > + ALT_CMO_OP(INVAL, vaddr, size, riscv_cbom_block_size); > } > > static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size) > @@ -59,7 +59,7 @@ static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size) > } > #endif > > - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); > + ALT_CMO_OP(FLUSH, vaddr, size, riscv_cbom_block_size); > } > > static inline bool arch_sync_dma_clean_before_fromdevice(void) > @@ -131,7 +131,7 @@ void arch_dma_prep_coherent(struct page *page, size_t size) > } > #endif > > - ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); > + ALT_CMO_OP(FLUSH, flush_addr, size, riscv_cbom_block_size); > } > > void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, > diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c > index c5fc5ec96f6d..370a422ede11 100644 > --- a/arch/riscv/mm/pmem.c > +++ b/arch/riscv/mm/pmem.c > @@ -17,7 +17,7 @@ void arch_wb_cache_pmem(void *addr, size_t size) > return; > } > #endif > - ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size); > + ALT_CMO_OP(CLEAN, addr, size, riscv_cbom_block_size); > } > EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); > > @@ -29,6 +29,6 @@ void arch_invalidate_pmem(void *addr, size_t size) > return; > } > #endif > - ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size); > + ALT_CMO_OP(INVAL, addr, size, riscv_cbom_block_size); > } > EXPORT_SYMBOL_GPL(arch_invalidate_pmem); > -- > 2.39.2 > If it compiles, ship it :-) Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Thanks, drew
Hello: This patch was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Fri, 15 Sep 2023 16:40:44 +0100 you wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The CMO op macros initially used lower case, as the original iteration > of the ALT_CMO_OP alternative stringified the first parameter to > finalise the assembly for the standard variant. > As a knock-on, the T-Head versions of these CMOs had to use mixed case > defines. Commit dd23e9535889 ("RISC-V: replace cbom instructions with > an insn-def") removed the asm construction with stringify, replacing it > an insn-def macro, rending the lower-case surplus to requirements. > As far as I can tell from a brief check, CBO_zero does not see similar > use and didn't require the mixed case define in the first place. > Replace the lower case characters now for consistency with other > insn-def macros in the standard and T-Head forms, and adjust the > callsites. > > [...] Here is the summary with links: - [v1] RISC-V: capitalise CMO op macros https://git.kernel.org/riscv/c/d3eabf2f2c81 You are awesome, thank you!
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index e2ecd01bfac7..5801af83d154 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -117,9 +117,9 @@ asm volatile(ALTERNATIVE( \ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000000 11001 00000 000 00000 0001011 */ -#define THEAD_inval_A0 ".long 0x0265000b" -#define THEAD_clean_A0 ".long 0x0245000b" -#define THEAD_flush_A0 ".long 0x0275000b" +#define THEAD_INVAL_A0 ".long 0x0265000b" +#define THEAD_CLEAN_A0 ".long 0x0245000b" +#define THEAD_FLUSH_A0 ".long 0x0275000b" #define THEAD_SYNC_S ".long 0x0190000b" #define ALT_CMO_OP(_op, _start, _size, _cachesize) \ diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h index 6960beb75f32..e27179b26086 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -180,19 +180,19 @@ INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(51), \ __RD(0), RS1(gaddr), RS2(vmid)) -#define CBO_inval(base) \ +#define CBO_INVAL(base) \ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ RS1(base), SIMM12(0)) -#define CBO_clean(base) \ +#define CBO_CLEAN(base) \ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ RS1(base), SIMM12(1)) -#define CBO_flush(base) \ +#define CBO_FLUSH(base) \ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ RS1(base), SIMM12(2)) -#define CBO_zero(base) \ +#define CBO_ZERO(base) \ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ RS1(base), SIMM12(4)) diff --git a/arch/riscv/lib/clear_page.S b/arch/riscv/lib/clear_page.S index d7a256eb53f4..b22de1231144 100644 --- a/arch/riscv/lib/clear_page.S +++ b/arch/riscv/lib/clear_page.S @@ -29,41 +29,41 @@ SYM_FUNC_START(clear_page) lw a1, riscv_cboz_block_size add a2, a0, a2 .Lzero_loop: - CBO_zero(a0) + CBO_ZERO(a0) add a0, a0, a1 CBOZ_ALT(11, "bltu a0, a2, .Lzero_loop; ret", "nop; nop") - CBO_zero(a0) + CBO_ZERO(a0) add a0, a0, a1 CBOZ_ALT(10, "bltu a0, a2, .Lzero_loop; ret", "nop; nop") - CBO_zero(a0) + CBO_ZERO(a0) add a0, a0, a1 - CBO_zero(a0) + CBO_ZERO(a0) add a0, a0, a1 CBOZ_ALT(9, "bltu a0, a2, .Lzero_loop; ret", "nop; nop") - CBO_zero(a0) + CBO_ZERO(a0) add a0, a0, a1 - CBO_zero(a0) + CBO_ZERO(a0) add a0, a0, a1 - CBO_zero(a0) + CBO_ZERO(a0) add a0, a0, a1 - CBO_zero(a0) + CBO_ZERO(a0) add a0, a0, a1 CBOZ_ALT(8, "bltu a0, a2, .Lzero_loop; ret", "nop; nop") - CBO_zero(a0) + CBO_ZERO(a0) add a0, a0, a1 - CBO_zero(a0) + CBO_ZERO(a0) add a0, a0, a1 - CBO_zero(a0) + CBO_ZERO(a0) add a0, a0, a1 - CBO_zero(a0) + CBO_ZERO(a0) add a0, a0, a1 - CBO_zero(a0) + CBO_ZERO(a0) add a0, a0, a1 - CBO_zero(a0) + CBO_ZERO(a0) add a0, a0, a1 - CBO_zero(a0) + CBO_ZERO(a0) add a0, a0, a1 - CBO_zero(a0) + CBO_ZERO(a0) add a0, a0, a1 bltu a0, a2, .Lzero_loop ret diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index b76e7e192eb1..607d5f47d437 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -31,7 +31,7 @@ static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size) return; } #endif - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(CLEAN, vaddr, size, riscv_cbom_block_size); } static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size) @@ -45,7 +45,7 @@ static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size) } #endif - ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(INVAL, vaddr, size, riscv_cbom_block_size); } static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size) @@ -59,7 +59,7 @@ static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size) } #endif - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(FLUSH, vaddr, size, riscv_cbom_block_size); } static inline bool arch_sync_dma_clean_before_fromdevice(void) @@ -131,7 +131,7 @@ void arch_dma_prep_coherent(struct page *page, size_t size) } #endif - ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); + ALT_CMO_OP(FLUSH, flush_addr, size, riscv_cbom_block_size); } void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c index c5fc5ec96f6d..370a422ede11 100644 --- a/arch/riscv/mm/pmem.c +++ b/arch/riscv/mm/pmem.c @@ -17,7 +17,7 @@ void arch_wb_cache_pmem(void *addr, size_t size) return; } #endif - ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size); + ALT_CMO_OP(CLEAN, addr, size, riscv_cbom_block_size); } EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); @@ -29,6 +29,6 @@ void arch_invalidate_pmem(void *addr, size_t size) return; } #endif - ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size); + ALT_CMO_OP(INVAL, addr, size, riscv_cbom_block_size); } EXPORT_SYMBOL_GPL(arch_invalidate_pmem);