| Message ID | 20231018222441.4131237-2-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/lnl: Assign correct phys | expand |
Quoting Lucas De Marchi (2023-10-18 19:24:40-03:00) >For Lunar Lake, DDI-A is connected to C10 PHY, while TC1-TC3 are connected >to C20 phy, like in Meteor Lake. Update the check in intel_is_c10phy() >accordingly. > >This reverts the change in commit e388ae97e225 ("drm/i915/display: >Eliminate IS_METEORLAKE checks") that turned that into a display engine >version check. The phy <-> port connection is very SoC-specific and not >related to that version. > >IS_LUNARLAKE() is defined to 0 in i915 as it's expected that the >(upcoming) xe driver is the one defining the platform, with i915 only >driving the display side. > >Bspec: 70818 >Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> >--- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c >index d414f6b7f993..e775f4721158 100644 >--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c >+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c >@@ -31,7 +31,7 @@ > > bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy) > { >- if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0) && phy < PHY_C) >+ if ((IS_LUNARLAKE(i915) || IS_METEORLAKE(i915)) && phy < PHY_C) > return true; > > return false; >diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >index 6a2a78c61f21..259884b10d9a 100644 >--- a/drivers/gpu/drm/i915/i915_drv.h >+++ b/drivers/gpu/drm/i915/i915_drv.h >@@ -575,6 +575,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) > #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO) > #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) >+#define IS_LUNARLAKE(i915) 0 > > #define IS_DG2_G10(i915) \ > IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) >-- >2.40.1 >
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index d414f6b7f993..e775f4721158 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -31,7 +31,7 @@ bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy) { - if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0) && phy < PHY_C) + if ((IS_LUNARLAKE(i915) || IS_METEORLAKE(i915)) && phy < PHY_C) return true; return false; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6a2a78c61f21..259884b10d9a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -575,6 +575,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO) #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) +#define IS_LUNARLAKE(i915) 0 #define IS_DG2_G10(i915) \ IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
For Lunar Lake, DDI-A is connected to C10 PHY, while TC1-TC3 are connected to C20 phy, like in Meteor Lake. Update the check in intel_is_c10phy() accordingly. This reverts the change in commit e388ae97e225 ("drm/i915/display: Eliminate IS_METEORLAKE checks") that turned that into a display engine version check. The phy <-> port connection is very SoC-specific and not related to that version. IS_LUNARLAKE() is defined to 0 in i915 as it's expected that the (upcoming) xe driver is the one defining the platform, with i915 only driving the display side. Bspec: 70818 Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)