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[v2,0/2] drm/i915/lnl: Assign correct phys

Message ID 20231026184045.1015655-1-lucas.demarchi@intel.com (mailing list archive)
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Series drm/i915/lnl: Assign correct phys | expand

Message

Lucas De Marchi Oct. 26, 2023, 6:40 p.m. UTC
For this series to work, we still need a separate patch on the xe side
so it defines the LNL platform macro to be used by display.

One thing missing for LNL during the previous patches was the
port <-> phy assignment. With the bspec now clarified, this is the
minimum changes needed for LNL.  As the commit messages say and after
looking at the history of the code, it seems we were thinking to go one
direction abstraction-wise with DG2, but reverted course with MTL. The
end result right now is a very confusing mix of port/phy/tc_port.
I was hoping to do a cleanup now, but we probably need some consensus on
the approach as it'd be an intrusive change.

Here are some thoughts after looking again at the current state of the
code:

1) What is the port -> phy conversion for? AFAIR this was because from
the display engine side we want, some registers have bit offsets based
on the port and others are based on the PHY. I think now we can

	a) Remove enum tc_port and have only `enum port` and `enum phy`.
	   Those should be sufficient for all platform needs afaics

	b) Add phy to intel_encoder (or intel_digital_port). It's
	   appalling number of places we convert from port to phy. That
	   would just be initialized during init.

2) It looks we need to better abstract the phy handling. Right now it's
very confusing with dkl, c10/c20 (that leak the abstraction from
intel_cx0_phy.c to everywhere in the driver), snps and the older
combo/tc being a superset of them.  I'm still not sure what to do here.
One thing that we can probably do is to remove the dg2-special case and
let the "is tc" be about the **port being connected to a TC-capable phy**.
Bspec always refer to those as TC<N> / USBC<N>. Then dkl, c10, c20, snps
would all be in the same abstraction layer.


Lucas De Marchi (2):
  drm/i915/lnl: Extend C10/C20 phy
  Subject: [PATCH] drm/i915/lnl: Fix check for TC phy

 drivers/gpu/drm/i915/display/intel_cx0_phy.c |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c | 28 ++++++++++----------
 drivers/gpu/drm/i915/i915_drv.h              |  1 +
 3 files changed, 16 insertions(+), 15 deletions(-)

Comments

Lucas De Marchi Oct. 29, 2023, 11:43 p.m. UTC | #1
On Sat, Oct 28, 2023 at 03:06:40PM +0000, Patchwork wrote:
>== Series Details ==
>
>Series: drm/i915/lnl: Assign correct phys (rev3)
>URL   : https://patchwork.freedesktop.org/series/125322/
>State : failure
>
>== Summary ==
>
>CI Bug Log - changes from CI_DRM_13799_full -> Patchwork_125322v3_full
>====================================================
>
>Summary
>-------
>
>  **FAILURE**
>
>  Serious unknown changes coming with Patchwork_125322v3_full absolutely need to be
>  verified manually.
>
>  If you think the reported changes have nothing to do with the changes
>  introduced in Patchwork_125322v3_full, please notify your bug team (lgci.bug.filing@intel.com) to allow them
>  to document this new failure mode, which will reduce false positives in CI.
>
>
>
>Participating hosts (12 -> 12)
>------------------------------
>
>  No changes in participating hosts
>
>Possible new issues
>-------------------
>
>  Here are the unknown changes that may have been introduced in Patchwork_125322v3_full:
>
>### IGT changes ###
>
>#### Possible regressions ####
>
>  * igt@gem_eio@reset-stress:
>    - shard-tglu:         [PASS][1] -> [FAIL][2]
>   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13799/shard-tglu-5/igt@gem_eio@reset-stress.html
>   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125322v3/shard-tglu-5/igt@gem_eio@reset-stress.html
>
>  * igt@syncobj_timeline@invalid-multi-wait-all-available-unsubmitted-submitted-signaled:
>    - shard-glk:          NOTRUN -> [FAIL][3]
>   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125322v3/shard-glk9/igt@syncobj_timeline@invalid-multi-wait-all-available-unsubmitted-submitted-signaled.html
>
>  * igt@syncobj_timeline@invalid-multi-wait-available-unsubmitted-submitted-signaled:
>    - shard-rkl:          NOTRUN -> [FAIL][4]
>   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125322v3/shard-rkl-1/igt@syncobj_timeline@invalid-multi-wait-available-unsubmitted-submitted-signaled.html


none of these are related to these display patches. Patches applied to
drm-intel-next. Thanks for the reviews

Lucas De Marchi