| Message ID | 20231026151828.754279-8-max.chou@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update RISC-V vector crypto to ratified v1.0.0 | expand |
On 10/26/23 12:18, Max Chou wrote: > Expose the properties of NIST Algorithm Suite related extensions (Zvkn, > Zvknc, Zvkng). > > Signed-off-by: Max Chou <max.chou@sifive.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 992f8e0f7b0..8eae8d3e59c 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -127,7 +127,10 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), > ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb), > ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), > + ISA_EXT_DATA_ENTRY(zvkn, PRIV_VERSION_1_12_0, ext_zvkn), > + ISA_EXT_DATA_ENTRY(zvknc, PRIV_VERSION_1_12_0, ext_zvknc), > ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), > + ISA_EXT_DATA_ENTRY(zvkng, PRIV_VERSION_1_12_0, ext_zvkng), > ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), > ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), > ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), > @@ -1379,6 +1382,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false), > MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false), > MULTI_EXT_CFG_BOOL("x-zvkt", ext_zvkt, false), > + MULTI_EXT_CFG_BOOL("x-zvkn", ext_zvkn, false), > + MULTI_EXT_CFG_BOOL("x-zvknc", ext_zvknc, false), > + MULTI_EXT_CFG_BOOL("x-zvkng", ext_zvkng, false), > > DEFINE_PROP_END_OF_LIST(), > };
On Fri, Oct 27, 2023 at 1:21 AM Max Chou <max.chou@sifive.com> wrote: > > Expose the properties of NIST Algorithm Suite related extensions (Zvkn, > Zvknc, Zvkng). > > Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 992f8e0f7b0..8eae8d3e59c 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -127,7 +127,10 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), > ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb), > ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), > + ISA_EXT_DATA_ENTRY(zvkn, PRIV_VERSION_1_12_0, ext_zvkn), > + ISA_EXT_DATA_ENTRY(zvknc, PRIV_VERSION_1_12_0, ext_zvknc), > ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), > + ISA_EXT_DATA_ENTRY(zvkng, PRIV_VERSION_1_12_0, ext_zvkng), > ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), > ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), > ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), > @@ -1379,6 +1382,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false), > MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false), > MULTI_EXT_CFG_BOOL("x-zvkt", ext_zvkt, false), > + MULTI_EXT_CFG_BOOL("x-zvkn", ext_zvkn, false), > + MULTI_EXT_CFG_BOOL("x-zvknc", ext_zvknc, false), > + MULTI_EXT_CFG_BOOL("x-zvkng", ext_zvkng, false), > > DEFINE_PROP_END_OF_LIST(), > }; > -- > 2.34.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 992f8e0f7b0..8eae8d3e59c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -127,7 +127,10 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb), ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), + ISA_EXT_DATA_ENTRY(zvkn, PRIV_VERSION_1_12_0, ext_zvkn), + ISA_EXT_DATA_ENTRY(zvknc, PRIV_VERSION_1_12_0, ext_zvknc), ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), + ISA_EXT_DATA_ENTRY(zvkng, PRIV_VERSION_1_12_0, ext_zvkng), ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), @@ -1379,6 +1382,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false), MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false), MULTI_EXT_CFG_BOOL("x-zvkt", ext_zvkt, false), + MULTI_EXT_CFG_BOOL("x-zvkn", ext_zvkn, false), + MULTI_EXT_CFG_BOOL("x-zvknc", ext_zvknc, false), + MULTI_EXT_CFG_BOOL("x-zvkng", ext_zvkng, false), DEFINE_PROP_END_OF_LIST(), };
Expose the properties of NIST Algorithm Suite related extensions (Zvkn, Zvknc, Zvkng). Signed-off-by: Max Chou <max.chou@sifive.com> --- target/riscv/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+)