| Message ID | 20231029042712.520010-10-cristian.ciocaltea@collabora.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | Enable networking support for StarFive JH7100 SoC | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
Cristian Ciocaltea wrote: > Provide the sysmain and gmac DT nodes supporting the DWMAC found on the > StarFive JH7100 SoC. > > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> > --- > arch/riscv/boot/dts/starfive/jh7100.dtsi | 36 ++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi > index a8a5bb00b0d8..e8228e96d350 100644 > --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi > @@ -179,6 +179,37 @@ plic: interrupt-controller@c000000 { > riscv,ndev = <133>; > }; > > + gmac: ethernet@10020000 { > + compatible = "starfive,jh7100-dwmac", "snps,dwmac"; > + reg = <0x0 0x10020000 0x0 0x10000>; > + clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>, > + <&clkgen JH7100_CLK_GMAC_AHB>, > + <&clkgen JH7100_CLK_GMAC_PTP_REF>, > + <&clkgen JH7100_CLK_GMAC_TX_INV>, > + <&clkgen JH7100_CLK_GMAC_GTX>; > + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx"; > + resets = <&rstgen JH7100_RSTN_GMAC_AHB>; > + reset-names = "ahb"; > + interrupts = <6>, <7>; > + interrupt-names = "macirq", "eth_wake_irq"; > + max-frame-size = <9000>; > + snps,multicast-filter-bins = <32>; > + snps,perfect-filter-entries = <128>; > + starfive,syscon = <&sysmain 0x70 0>; > + rx-fifo-depth = <32768>; > + tx-fifo-depth = <16384>; > + snps,axi-config = <&stmmac_axi_setup>; > + snps,fixed-burst; > + snps,force_thresh_dma_mode; > + status = "disabled"; > + > + stmmac_axi_setup: stmmac-axi-config { > + snps,wr_osr_lmt = <0xf>; > + snps,rd_osr_lmt = <0xf>; As I also noted on the JH7110 patches these are not addresses or offsets but limits eg. counting things, which makes a lot more sense in decimal for most humans. But here you've changed them back to 0xf, why? > + snps,blen = <256 128 64 32 0 0 0>; > + }; > + }; > + > clkgen: clock-controller@11800000 { > compatible = "starfive,jh7100-clkgen"; > reg = <0x0 0x11800000 0x0 0x10000>; > @@ -193,6 +224,11 @@ rstgen: reset-controller@11840000 { > #reset-cells = <1>; > }; > > + sysmain: syscon@11850000 { > + compatible = "starfive,jh7100-sysmain", "syscon"; > + reg = <0x0 0x11850000 0x0 0x10000>; > + }; > + > i2c0: i2c@118b0000 { > compatible = "snps,designware-i2c"; > reg = <0x0 0x118b0000 0x0 0x10000>; > -- > 2.42.0 >
On 11/26/23 23:15, Emil Renner Berthing wrote: > Cristian Ciocaltea wrote: >> Provide the sysmain and gmac DT nodes supporting the DWMAC found on the >> StarFive JH7100 SoC. >> >> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> >> --- >> arch/riscv/boot/dts/starfive/jh7100.dtsi | 36 ++++++++++++++++++++++++ >> 1 file changed, 36 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi >> index a8a5bb00b0d8..e8228e96d350 100644 >> --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi >> +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi >> @@ -179,6 +179,37 @@ plic: interrupt-controller@c000000 { >> riscv,ndev = <133>; >> }; >> >> + gmac: ethernet@10020000 { >> + compatible = "starfive,jh7100-dwmac", "snps,dwmac"; >> + reg = <0x0 0x10020000 0x0 0x10000>; >> + clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>, >> + <&clkgen JH7100_CLK_GMAC_AHB>, >> + <&clkgen JH7100_CLK_GMAC_PTP_REF>, >> + <&clkgen JH7100_CLK_GMAC_TX_INV>, >> + <&clkgen JH7100_CLK_GMAC_GTX>; >> + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx"; >> + resets = <&rstgen JH7100_RSTN_GMAC_AHB>; >> + reset-names = "ahb"; >> + interrupts = <6>, <7>; >> + interrupt-names = "macirq", "eth_wake_irq"; >> + max-frame-size = <9000>; >> + snps,multicast-filter-bins = <32>; >> + snps,perfect-filter-entries = <128>; >> + starfive,syscon = <&sysmain 0x70 0>; >> + rx-fifo-depth = <32768>; >> + tx-fifo-depth = <16384>; >> + snps,axi-config = <&stmmac_axi_setup>; >> + snps,fixed-burst; >> + snps,force_thresh_dma_mode; >> + status = "disabled"; >> + >> + stmmac_axi_setup: stmmac-axi-config { >> + snps,wr_osr_lmt = <0xf>; >> + snps,rd_osr_lmt = <0xf>; > > As I also noted on the JH7110 patches these are not addresses or offsets but > limits eg. counting things, which makes a lot more sense in decimal for most > humans. But here you've changed them back to 0xf, why? That's a left over from v1. Will fix, thanks! >> + snps,blen = <256 128 64 32 0 0 0>; >> + }; >> + }; >> + >> clkgen: clock-controller@11800000 { >> compatible = "starfive,jh7100-clkgen"; >> reg = <0x0 0x11800000 0x0 0x10000>; >> @@ -193,6 +224,11 @@ rstgen: reset-controller@11840000 { >> #reset-cells = <1>; >> }; >> >> + sysmain: syscon@11850000 { >> + compatible = "starfive,jh7100-sysmain", "syscon"; >> + reg = <0x0 0x11850000 0x0 0x10000>; >> + }; >> + >> i2c0: i2c@118b0000 { >> compatible = "snps,designware-i2c"; >> reg = <0x0 0x118b0000 0x0 0x10000>; >> -- >> 2.42.0 >>
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index a8a5bb00b0d8..e8228e96d350 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -179,6 +179,37 @@ plic: interrupt-controller@c000000 { riscv,ndev = <133>; }; + gmac: ethernet@10020000 { + compatible = "starfive,jh7100-dwmac", "snps,dwmac"; + reg = <0x0 0x10020000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>, + <&clkgen JH7100_CLK_GMAC_AHB>, + <&clkgen JH7100_CLK_GMAC_PTP_REF>, + <&clkgen JH7100_CLK_GMAC_TX_INV>, + <&clkgen JH7100_CLK_GMAC_GTX>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx"; + resets = <&rstgen JH7100_RSTN_GMAC_AHB>; + reset-names = "ahb"; + interrupts = <6>, <7>; + interrupt-names = "macirq", "eth_wake_irq"; + max-frame-size = <9000>; + snps,multicast-filter-bins = <32>; + snps,perfect-filter-entries = <128>; + starfive,syscon = <&sysmain 0x70 0>; + rx-fifo-depth = <32768>; + tx-fifo-depth = <16384>; + snps,axi-config = <&stmmac_axi_setup>; + snps,fixed-burst; + snps,force_thresh_dma_mode; + status = "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <256 128 64 32 0 0 0>; + }; + }; + clkgen: clock-controller@11800000 { compatible = "starfive,jh7100-clkgen"; reg = <0x0 0x11800000 0x0 0x10000>; @@ -193,6 +224,11 @@ rstgen: reset-controller@11840000 { #reset-cells = <1>; }; + sysmain: syscon@11850000 { + compatible = "starfive,jh7100-sysmain", "syscon"; + reg = <0x0 0x11850000 0x0 0x10000>; + }; + i2c0: i2c@118b0000 { compatible = "snps,designware-i2c"; reg = <0x0 0x118b0000 0x0 0x10000>;
Provide the sysmain and gmac DT nodes supporting the DWMAC found on the StarFive JH7100 SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+)