| Message ID | 20240118090413.130989-2-pkshih@realtek.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Kalle Valo |
| Headers | show |
| Series | wifi: rtw89: 8922a: implement more chip_ops for 8922A | expand |
Ping-Ke Shih <pkshih@realtek.com> wrote: > WiFi 7 chips can operate in various MLO applications, such as 1 link (2SS) > and 2 links (1SS + 1SS), and we should configure different PHY mode for > each of them. > > For example, > - MLO_2_PLUS_0_1RF is 1 link with 2SS rate, and enable one RF component. > - MLO_1_PLUS_1_1RF is 2 links with 1SS rate for each, and enable one RF > component that can support two paths. > > By default, we set the mode to legacy MLO_DBCC_NOT_SUPPORT (don't support > MLO and DBCC yet), and later we will introduce logic to change the mode. > > Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Failed to apply: error: sha1 information is lacking or useless (drivers/net/wireless/realtek/rtw89/rtw8922a.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Applying: wifi: rtw89: 8922a: add TX power related ops Patch failed at 0001 wifi: rtw89: 8922a: add TX power related ops 6 patches set to Changes Requested. 13522603 [v2,1/6] wifi: rtw89: add mlo_dbcc_mode for WiFi 7 chips 13522604 [v2,2/6] wifi: rtw89: 8922a: add chip_ops::{enable,disable}_bb_rf 13522605 [v2,3/6] wifi: rtw89: 8922a: add chip_ops related to BB init 13522606 [v2,4/6] wifi: rtw89: 8922a: add register definitions of H2C, C2H, page, RRSR and EDCCA 13522607 [v2,5/6] wifi: rtw89: 8922a: add TX power related ops 13522608 [v2,6/6] wifi: rtw89: 8922a: add BTG functions to assist BT coexistence to control TX/RX
diff --git a/drivers/net/wireless/realtek/rtw89/core.c b/drivers/net/wireless/realtek/rtw89/core.c index fd527a249996..6dcdc46b2345 100644 --- a/drivers/net/wireless/realtek/rtw89/core.c +++ b/drivers/net/wireless/realtek/rtw89/core.c @@ -4078,6 +4078,8 @@ int rtw89_core_init(struct rtw89_dev *rtwdev) rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; + rtwdev->dbcc_en = false; + rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT; INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h index 662425ba395b..816eec15f760 100644 --- a/drivers/net/wireless/realtek/rtw89/core.h +++ b/drivers/net/wireless/realtek/rtw89/core.h @@ -3226,6 +3226,20 @@ enum rtw89_dma_ch { RTW89_DMA_CH_NUM = 13 }; +#define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) + +enum rtw89_mlo_dbcc_mode { + MLO_DBCC_NOT_SUPPORT = 1, + MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), + MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), + MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), + MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), + MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), + MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), + MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), + DBCC_LEGACY = 0xffffffff, +}; + enum rtw89_qta_mode { RTW89_QTA_SCC, RTW89_QTA_DLFW, @@ -4821,6 +4835,7 @@ struct rtw89_dev { const struct ieee80211_ops *ops; bool dbcc_en; + enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; struct rtw89_hw_scan_info scan_info; const struct rtw89_chip_info *chip; const struct rtw89_pci_info *pci_info; @@ -5817,6 +5832,18 @@ static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, rcu_read_unlock(); } +static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) +{ + switch (rtwdev->mlo_dbcc_mode) { + case MLO_1_PLUS_1_1RF: + case MLO_1_PLUS_1_2RF: + case DBCC_LEGACY: + return true; + default: + return false; + } +} + int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
WiFi 7 chips can operate in various MLO applications, such as 1 link (2SS) and 2 links (1SS + 1SS), and we should configure different PHY mode for each of them. For example, - MLO_2_PLUS_0_1RF is 1 link with 2SS rate, and enable one RF component. - MLO_1_PLUS_1_1RF is 2 links with 1SS rate for each, and enable one RF component that can support two paths. By default, we set the mode to legacy MLO_DBCC_NOT_SUPPORT (don't support MLO and DBCC yet), and later we will introduce logic to change the mode. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> --- drivers/net/wireless/realtek/rtw89/core.c | 2 ++ drivers/net/wireless/realtek/rtw89/core.h | 27 +++++++++++++++++++++++ 2 files changed, 29 insertions(+)