Message ID | 1705669223-5655-3-git-send-email-quic_msarkar@quicinc.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | Add Change to integrate HDMA with dwc ep driver | expand |
On Fri, 19 Jan 2024 at 15:00, Mrinmay Sarkar <quic_msarkar@quicinc.com> wrote: > > From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > Add common helpers for getting the eDMA/HDMA max channel count. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> > --- > drivers/dma/dw-edma/dw-edma-core.c | 18 ++++++++++++++++++ > drivers/pci/controller/dwc/pcie-designware.c | 6 +++--- > include/linux/dma/edma.h | 14 ++++++++++++++ > 3 files changed, 35 insertions(+), 3 deletions(-) > > diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c > index 7fe1c19..2bd6e43 100644 > --- a/drivers/dma/dw-edma/dw-edma-core.c > +++ b/drivers/dma/dw-edma/dw-edma-core.c > @@ -902,6 +902,24 @@ static int dw_edma_irq_request(struct dw_edma *dw, > return err; > } > > +static u32 dw_edma_get_max_ch(enum dw_edma_map_format mf, enum dw_edma_dir dir) > +{ > + if (mf == EDMA_MF_HDMA_NATIVE) > + return HDMA_MAX_NR_CH; This will break unless patch 5 is applied. Please move the corresponding definition to this path. > + > + return dir == EDMA_DIR_WRITE ? EDMA_MAX_WR_CH : EDMA_MAX_RD_CH; > +} > + > +u32 dw_edma_get_max_rd_ch(enum dw_edma_map_format mf) > +{ > + return dw_edma_get_max_ch(mf, EDMA_DIR_READ); > +} > + > +u32 dw_edma_get_max_wr_ch(enum dw_edma_map_format mf) > +{ > + return dw_edma_get_max_ch(mf, EDMA_DIR_WRITE); > +} > + > int dw_edma_probe(struct dw_edma_chip *chip) > { > struct device *dev;
On Fri, Jan 19, 2024 at 03:26:56PM +0200, Dmitry Baryshkov wrote: > On Fri, 19 Jan 2024 at 15:00, Mrinmay Sarkar <quic_msarkar@quicinc.com> wrote: > > > > From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > > > Add common helpers for getting the eDMA/HDMA max channel count. > > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> > > --- > > drivers/dma/dw-edma/dw-edma-core.c | 18 ++++++++++++++++++ > > drivers/pci/controller/dwc/pcie-designware.c | 6 +++--- > > include/linux/dma/edma.h | 14 ++++++++++++++ > > 3 files changed, 35 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c > > index 7fe1c19..2bd6e43 100644 > > --- a/drivers/dma/dw-edma/dw-edma-core.c > > +++ b/drivers/dma/dw-edma/dw-edma-core.c > > @@ -902,6 +902,24 @@ static int dw_edma_irq_request(struct dw_edma *dw, > > return err; > > } > > > > +static u32 dw_edma_get_max_ch(enum dw_edma_map_format mf, enum dw_edma_dir dir) > > +{ > > + if (mf == EDMA_MF_HDMA_NATIVE) > > + return HDMA_MAX_NR_CH; > > This will break unless patch 5 is applied. I believe you are referring to patch 4. > Please move the > corresponding definition to this path. > Right. But it can be fixed by reordering the patches. Mrinmay, please move patch 4/6 ahead of this one. - Mani
On Fri, Jan 19, 2024 at 06:30:18PM +0530, Mrinmay Sarkar wrote: > From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > Add common helpers for getting the eDMA/HDMA max channel count. See my comment to the patch 4: https://lore.kernel.org/linux-pci/qfdsnz7louqdrs6mhz72o6mzjo66kw63vtlhgpz6hgqfyyzyhq@tge3r7mvwtw3/ -Serge(y) > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> > --- > drivers/dma/dw-edma/dw-edma-core.c | 18 ++++++++++++++++++ > drivers/pci/controller/dwc/pcie-designware.c | 6 +++--- > include/linux/dma/edma.h | 14 ++++++++++++++ > 3 files changed, 35 insertions(+), 3 deletions(-) > > diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c > index 7fe1c19..2bd6e43 100644 > --- a/drivers/dma/dw-edma/dw-edma-core.c > +++ b/drivers/dma/dw-edma/dw-edma-core.c > @@ -902,6 +902,24 @@ static int dw_edma_irq_request(struct dw_edma *dw, > return err; > } > > +static u32 dw_edma_get_max_ch(enum dw_edma_map_format mf, enum dw_edma_dir dir) > +{ > + if (mf == EDMA_MF_HDMA_NATIVE) > + return HDMA_MAX_NR_CH; > + > + return dir == EDMA_DIR_WRITE ? EDMA_MAX_WR_CH : EDMA_MAX_RD_CH; > +} > + > +u32 dw_edma_get_max_rd_ch(enum dw_edma_map_format mf) > +{ > + return dw_edma_get_max_ch(mf, EDMA_DIR_READ); > +} > + > +u32 dw_edma_get_max_wr_ch(enum dw_edma_map_format mf) > +{ > + return dw_edma_get_max_ch(mf, EDMA_DIR_WRITE); > +} > + > int dw_edma_probe(struct dw_edma_chip *chip) > { > struct device *dev; > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index eca047a..96575b8 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -864,7 +864,7 @@ static int dw_pcie_edma_irq_vector(struct dw_edma_chip *edma, unsigned int nr) > char name[6]; > int ret; > > - if (nr >= EDMA_MAX_WR_CH + EDMA_MAX_RD_CH) > + if (nr >= dw_edma_get_max_rd_ch(edma->mf) + dw_edma_get_max_wr_ch(edma->mf)) > return -EINVAL; > > ret = platform_get_irq_byname_optional(pdev, "dma"); > @@ -923,8 +923,8 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci) > pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); > > /* Sanity check the channels count if the mapping was incorrect */ > - if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH || > - !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH) > + if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > dw_edma_get_max_wr_ch(pci->edma.mf) || > + !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > dw_edma_get_max_rd_ch(pci->edma.mf)) > return -EINVAL; > > return 0; > diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h > index 7197a58..550f6a4 100644 > --- a/include/linux/dma/edma.h > +++ b/include/linux/dma/edma.h > @@ -106,6 +106,9 @@ struct dw_edma_chip { > #if IS_REACHABLE(CONFIG_DW_EDMA) > int dw_edma_probe(struct dw_edma_chip *chip); > int dw_edma_remove(struct dw_edma_chip *chip); > + > +u32 dw_edma_get_max_rd_ch(enum dw_edma_map_format mf); > +u32 dw_edma_get_max_wr_ch(enum dw_edma_map_format mf); > #else > static inline int dw_edma_probe(struct dw_edma_chip *chip) > { > @@ -116,6 +119,17 @@ static inline int dw_edma_remove(struct dw_edma_chip *chip) > { > return 0; > } > + > +static inline u32 dw_edma_get_max_rd_ch(enum dw_edma_map_format mf) > +{ > + return 0; > +} > + > +static inline u32 dw_edma_get_max_wr_ch(enum dw_edma_map_format mf) > +{ > + return 0; > +} > + > #endif /* CONFIG_DW_EDMA */ > > #endif /* _DW_EDMA_H */ > -- > 2.7.4 >
diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index 7fe1c19..2bd6e43 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -902,6 +902,24 @@ static int dw_edma_irq_request(struct dw_edma *dw, return err; } +static u32 dw_edma_get_max_ch(enum dw_edma_map_format mf, enum dw_edma_dir dir) +{ + if (mf == EDMA_MF_HDMA_NATIVE) + return HDMA_MAX_NR_CH; + + return dir == EDMA_DIR_WRITE ? EDMA_MAX_WR_CH : EDMA_MAX_RD_CH; +} + +u32 dw_edma_get_max_rd_ch(enum dw_edma_map_format mf) +{ + return dw_edma_get_max_ch(mf, EDMA_DIR_READ); +} + +u32 dw_edma_get_max_wr_ch(enum dw_edma_map_format mf) +{ + return dw_edma_get_max_ch(mf, EDMA_DIR_WRITE); +} + int dw_edma_probe(struct dw_edma_chip *chip) { struct device *dev; diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index eca047a..96575b8 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -864,7 +864,7 @@ static int dw_pcie_edma_irq_vector(struct dw_edma_chip *edma, unsigned int nr) char name[6]; int ret; - if (nr >= EDMA_MAX_WR_CH + EDMA_MAX_RD_CH) + if (nr >= dw_edma_get_max_rd_ch(edma->mf) + dw_edma_get_max_wr_ch(edma->mf)) return -EINVAL; ret = platform_get_irq_byname_optional(pdev, "dma"); @@ -923,8 +923,8 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci) pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); /* Sanity check the channels count if the mapping was incorrect */ - if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH || - !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH) + if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > dw_edma_get_max_wr_ch(pci->edma.mf) || + !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > dw_edma_get_max_rd_ch(pci->edma.mf)) return -EINVAL; return 0; diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 7197a58..550f6a4 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -106,6 +106,9 @@ struct dw_edma_chip { #if IS_REACHABLE(CONFIG_DW_EDMA) int dw_edma_probe(struct dw_edma_chip *chip); int dw_edma_remove(struct dw_edma_chip *chip); + +u32 dw_edma_get_max_rd_ch(enum dw_edma_map_format mf); +u32 dw_edma_get_max_wr_ch(enum dw_edma_map_format mf); #else static inline int dw_edma_probe(struct dw_edma_chip *chip) { @@ -116,6 +119,17 @@ static inline int dw_edma_remove(struct dw_edma_chip *chip) { return 0; } + +static inline u32 dw_edma_get_max_rd_ch(enum dw_edma_map_format mf) +{ + return 0; +} + +static inline u32 dw_edma_get_max_wr_ch(enum dw_edma_map_format mf) +{ + return 0; +} + #endif /* CONFIG_DW_EDMA */ #endif /* _DW_EDMA_H */