| Message ID | 20240402103406.3638821-2-quic_varada@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add interconnect driver for IPQ9574 SoC | expand |
On 02/04/2024 12:34, Varadarajan Narayanan wrote: > +#define ICC_NSSNOC_NSSCC 10 > +#define ICC_NSSNOC_SNOC_0 11 > +#define ICC_NSSNOC_SNOC_1 12 > +#define ICC_NSSNOC_PCNOC_1 13 > +#define ICC_NSSNOC_QOSGEN_REF 14 > +#define ICC_NSSNOC_TIMEOUT_REF 15 > +#define ICC_NSSNOC_XO_DCD 16 > +#define ICC_NSSNOC_ATB 17 > +#define ICC_MEM_NOC_NSSNOC 18 > +#define ICC_NSSNOC_MEMNOC 19 > +#define ICC_NSSNOC_MEM_NOC_1 20 > + > +#define ICC_NSSNOC_PPE 0 > +#define ICC_NSSNOC_PPE_CFG 1 > +#define ICC_NSSNOC_NSS_CSR 2 > +#define ICC_NSSNOC_IMEM_QSB 3 > +#define ICC_NSSNOC_IMEM_AHB 4 > + > +#define MASTER(x) ((ICC_ ## x) * 2) > +#define SLAVE(x) (MASTER(x) + 1) You already received comment to make your bindings consistent with other Qualcomm bindings. Now you repeat the same mistake. No, that is neither consistent nor greppble. Best regards, Krzysztof
On Wed, Apr 03, 2024 at 09:09:15AM +0200, Krzysztof Kozlowski wrote: > On 02/04/2024 12:34, Varadarajan Narayanan wrote: > > +#define ICC_NSSNOC_NSSCC 10 > > +#define ICC_NSSNOC_SNOC_0 11 > > +#define ICC_NSSNOC_SNOC_1 12 > > +#define ICC_NSSNOC_PCNOC_1 13 > > +#define ICC_NSSNOC_QOSGEN_REF 14 > > +#define ICC_NSSNOC_TIMEOUT_REF 15 > > +#define ICC_NSSNOC_XO_DCD 16 > > +#define ICC_NSSNOC_ATB 17 > > +#define ICC_MEM_NOC_NSSNOC 18 > > +#define ICC_NSSNOC_MEMNOC 19 > > +#define ICC_NSSNOC_MEM_NOC_1 20 > > + > > +#define ICC_NSSNOC_PPE 0 > > +#define ICC_NSSNOC_PPE_CFG 1 > > +#define ICC_NSSNOC_NSS_CSR 2 > > +#define ICC_NSSNOC_IMEM_QSB 3 > > +#define ICC_NSSNOC_IMEM_AHB 4 > > + > > +#define MASTER(x) ((ICC_ ## x) * 2) > > +#define SLAVE(x) (MASTER(x) + 1) > > You already received comment to make your bindings consistent with other > Qualcomm bindings. Now you repeat the same mistake. > > No, that is neither consistent nor greppble. Sorry. Have restored the naming and posted v7. Kindly take a look. Thanks Varada
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml index 944a0ea79cd6..824781cbdf34 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml @@ -33,6 +33,9 @@ properties: - description: PCIE30 PHY3 pipe clock source - description: USB3 PHY pipe clock source + '#interconnect-cells': + const: 1 + required: - compatible - clocks diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h new file mode 100644 index 000000000000..988124c39810 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,ipq9574.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +#ifndef INTERCONNECT_QCOM_IPQ9574_H +#define INTERCONNECT_QCOM_IPQ9574_H + +#define ICC_ANOC_PCIE0 0 +#define ICC_SNOC_PCIE0 1 +#define ICC_ANOC_PCIE1 2 +#define ICC_SNOC_PCIE1 3 +#define ICC_ANOC_PCIE2 4 +#define ICC_SNOC_PCIE2 5 +#define ICC_ANOC_PCIE3 6 +#define ICC_SNOC_PCIE3 7 +#define ICC_SNOC_USB 8 +#define ICC_ANOC_USB_AXI 9 +#define ICC_NSSNOC_NSSCC 10 +#define ICC_NSSNOC_SNOC_0 11 +#define ICC_NSSNOC_SNOC_1 12 +#define ICC_NSSNOC_PCNOC_1 13 +#define ICC_NSSNOC_QOSGEN_REF 14 +#define ICC_NSSNOC_TIMEOUT_REF 15 +#define ICC_NSSNOC_XO_DCD 16 +#define ICC_NSSNOC_ATB 17 +#define ICC_MEM_NOC_NSSNOC 18 +#define ICC_NSSNOC_MEMNOC 19 +#define ICC_NSSNOC_MEM_NOC_1 20 + +#define ICC_NSSNOC_PPE 0 +#define ICC_NSSNOC_PPE_CFG 1 +#define ICC_NSSNOC_NSS_CSR 2 +#define ICC_NSSNOC_IMEM_QSB 3 +#define ICC_NSSNOC_IMEM_AHB 4 + +#define MASTER(x) ((ICC_ ## x) * 2) +#define SLAVE(x) (MASTER(x) + 1) + +#endif /* INTERCONNECT_QCOM_IPQ9574_H */
Add interconnect-cells to clock provider so that it can be used as icc provider. Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip interfaces. This will be used by the gcc-ipq9574 driver that will for providing interconnect services using the icc-clk framework. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> --- v6: Removed Reviewed-by: Krzysztof Kozlowski Redefine the bindings such that driver and DT can share them v3: Squash Documentation/ and include/ changes into same patch qcom,ipq9574.h Move 'first id' to clock driver --- .../bindings/clock/qcom,ipq9574-gcc.yaml | 3 ++ .../dt-bindings/interconnect/qcom,ipq9574.h | 36 +++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h