diff mbox series

[05/17] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller

Message ID 20240404122559.898930-6-peter.griffin@linaro.org (mailing list archive)
State New, archived
Headers show
Series HSI2, UFS & UFS phy support for Tensor GS101 | expand

Commit Message

Peter Griffin April 4, 2024, 12:25 p.m. UTC
Enable the cmu_hsi2 clock management unit. It feeds some of
the high speed interfaces such as PCIe and UFS.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

André Draszik April 5, 2024, 7:38 a.m. UTC | #1
On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> Enable the cmu_hsi2 clock management unit. It feeds some of
> the high speed interfaces such as PCIe and UFS.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index eddb6b326fde..38ac4fb1397e 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -1253,6 +1253,18 @@ pinctrl_hsi1: pinctrl@11840000 {
>  			interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
>  		};
>  
> +		cmu_hsi2: clock-controller@14400000 {
> +			compatible = "google,gs101-cmu-hsi2";
> +			reg = <0x14400000 0x4000>;
> +			#clock-cells = <1>;
> +			clocks = <&ext_24_5m>,
> +				 <&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
> +				 <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>,
> +				 <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
> +				 <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
> +			clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> +		};

This doesn't build because you didn't add the clock ids in the binding patch.

Other than that,

Reviewed-by: André Draszik <andre.draszik@linaro.org>

> +
>  		pinctrl_hsi2: pinctrl@14440000 {
>  			compatible = "google,gs101-pinctrl";
>  			reg = <0x14440000 0x00001000>;
Krzysztof Kozlowski April 5, 2024, 7:51 a.m. UTC | #2
On 04/04/2024 14:25, Peter Griffin wrote:
> Enable the cmu_hsi2 clock management unit. It feeds some of
> the high speed interfaces such as PCIe and UFS.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 


Was it really compiled?

Best regards,
Krzysztof
Peter Griffin April 16, 2024, 11:56 a.m. UTC | #3
Hi André,

Thanks for the review.

On Fri, 5 Apr 2024 at 08:38, André Draszik <andre.draszik@linaro.org> wrote:
>
> On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> > Enable the cmu_hsi2 clock management unit. It feeds some of
> > the high speed interfaces such as PCIe and UFS.
> >
> > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > ---
> >  arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > index eddb6b326fde..38ac4fb1397e 100644
> > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > @@ -1253,6 +1253,18 @@ pinctrl_hsi1: pinctrl@11840000 {
> >                       interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
> >               };
> >
> > +             cmu_hsi2: clock-controller@14400000 {
> > +                     compatible = "google,gs101-cmu-hsi2";
> > +                     reg = <0x14400000 0x4000>;
> > +                     #clock-cells = <1>;
> > +                     clocks = <&ext_24_5m>,
> > +                              <&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
> > +                              <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>,
> > +                              <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
> > +                              <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
> > +                     clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> > +             };
>
> This doesn't build because you didn't add the clock ids in the binding patch.

These clock IDs are for cmu_top, not cmu_hsi2. They were added as part
of the initial gs101/Oriole upstream support series in the following
commit

commit 0a910f1606384a5886a045e36b1fc80a7fa6706b
Author: Peter Griffin <peter.griffin@linaro.org>
Date:   Sat Dec 9 23:30:48 2023 +0000

    dt-bindings: clock: Add Google gs101 clock management unit bindings

    Provide dt-schema documentation for Google gs101 SoC clock controller.
    Currently this adds support for cmu_top, cmu_misc and cmu_apm.

    Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
    Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
    Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
    Link: https://lore.kernel.org/r/20231209233106.147416-3-peter.griffin@linaro.org
    Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

regards,

Peter
André Draszik April 16, 2024, 12:21 p.m. UTC | #4
Hi Pete,

On Tue, 2024-04-16 at 12:56 +0100, Peter Griffin wrote:
> Hi André,
> 
> Thanks for the review.
> 
> On Fri, 5 Apr 2024 at 08:38, André Draszik <andre.draszik@linaro.org> wrote:
> > 
> > On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> > > Enable the cmu_hsi2 clock management unit. It feeds some of
> > > the high speed interfaces such as PCIe and UFS.
> > > 
> > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > > ---
> > >  arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
> > >  1 file changed, 12 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > index eddb6b326fde..38ac4fb1397e 100644
> > > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > @@ -1253,6 +1253,18 @@ pinctrl_hsi1: pinctrl@11840000 {
> > >                       interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
> > >               };
> > > 
> > > +             cmu_hsi2: clock-controller@14400000 {
> > > +                     compatible = "google,gs101-cmu-hsi2";
> > > +                     reg = <0x14400000 0x4000>;
> > > +                     #clock-cells = <1>;
> > > +                     clocks = <&ext_24_5m>,
> > > +                              <&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
> > > +                              <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>,
> > > +                              <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
> > > +                              <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
> > > +                     clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> > > +             };
> > 
> > This doesn't build because you didn't add the clock ids in the binding patch.
> 
> These clock IDs are for cmu_top, not cmu_hsi2.

Right. I replied to the wrong patch. Sorry for that. It is patch 7 that
uses clock ids that are only added in patch 8. The clock ids from patch 8
in include/dt-bindings/clock/google,gs101.h should be added in patch 1
instead.

Cheers,
Andre'
Peter Griffin April 16, 2024, 2:33 p.m. UTC | #5
Hi André,

On Tue, 16 Apr 2024 at 13:21, André Draszik <andre.draszik@linaro.org> wrote:
>
> Hi Pete,
>
> On Tue, 2024-04-16 at 12:56 +0100, Peter Griffin wrote:
> > Hi André,
> >
> > Thanks for the review.
> >
> > On Fri, 5 Apr 2024 at 08:38, André Draszik <andre.draszik@linaro.org> wrote:
> > >
> > > On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> > > > Enable the cmu_hsi2 clock management unit. It feeds some of
> > > > the high speed interfaces such as PCIe and UFS.
> > > >
> > > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > > > ---
> > > >  arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
> > > >  1 file changed, 12 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > > index eddb6b326fde..38ac4fb1397e 100644
> > > > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > > @@ -1253,6 +1253,18 @@ pinctrl_hsi1: pinctrl@11840000 {
> > > >                       interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
> > > >               };
> > > >
> > > > +             cmu_hsi2: clock-controller@14400000 {
> > > > +                     compatible = "google,gs101-cmu-hsi2";
> > > > +                     reg = <0x14400000 0x4000>;
> > > > +                     #clock-cells = <1>;
> > > > +                     clocks = <&ext_24_5m>,
> > > > +                              <&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
> > > > +                              <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>,
> > > > +                              <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
> > > > +                              <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
> > > > +                     clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> > > > +             };
> > >
> > > This doesn't build because you didn't add the clock ids in the binding patch.
> >
> > These clock IDs are for cmu_top, not cmu_hsi2.
>
> Right. I replied to the wrong patch. Sorry for that. It is patch 7 that
> uses clock ids that are only added in patch 8. The clock ids from patch 8
> in include/dt-bindings/clock/google,gs101.h should be added in patch 1
> instead.

Ah I see, thanks for the clarification. I'll fix that in v2.

Thanks,

Pete
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index eddb6b326fde..38ac4fb1397e 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1253,6 +1253,18 @@  pinctrl_hsi1: pinctrl@11840000 {
 			interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
 		};
 
+		cmu_hsi2: clock-controller@14400000 {
+			compatible = "google,gs101-cmu-hsi2";
+			reg = <0x14400000 0x4000>;
+			#clock-cells = <1>;
+			clocks = <&ext_24_5m>,
+				 <&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
+				 <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>,
+				 <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
+				 <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
+			clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
+		};
+
 		pinctrl_hsi2: pinctrl@14440000 {
 			compatible = "google,gs101-pinctrl";
 			reg = <0x14440000 0x00001000>;