| Message ID | 20240425181610.2704633-1-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/xe/display: Fix ADL-N detection | expand |
On Thu, Apr 25, 2024 at 11:16:09AM -0700, Lucas De Marchi wrote: > Contrary to i915, in xe ADL-N is kept as a different platform, not a > subplatform of ADL-P. Since the display side doesn't need to > differentiate between P and N, i.e. IS_ALDERLAKE_P_N() is never called, > just fixup the compat header to check for both P and N. > > Moving ADL-N to be a subplatform would be more complex as the firmware > loading in xe only handles platforms, not subplatforms, as going forward > the direction is to check on IP version rather than > platforms/subplatforms. > > Fix warning when initializing display: > > xe 0000:00:02.0: [drm:intel_pch_type [xe]] Found Alder Lake PCH > ------------[ cut here ]------------ > xe 0000:00:02.0: drm_WARN_ON(!((dev_priv)->info.platform == XE_ALDERLAKE_S) && !((dev_priv)->info.platform == XE_ALDERLAKE_P)) > > And wrong paths being taken on the display side. > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> ADL-N uses exactly the same display IP as ADL-P (unlike on the GT side where they differ), so Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h > index ffaa4d2f1eed..cd4632276141 100644 > --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h > +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h > @@ -78,7 +78,8 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) > #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_ROCKETLAKE) > #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, XE_DG1) > #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_S) > -#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_P) > +#define IS_ALDERLAKE_P(dev_priv) (IS_PLATFORM(dev_priv, XE_ALDERLAKE_P) || \ > + IS_PLATFORM(dev_priv, XE_ALDERLAKE_N)) > #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2) > #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE) > #define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE) > -- > 2.43.0 >
On Thu, Apr 25, 2024 at 11:22:30AM GMT, Matt Roper wrote: >On Thu, Apr 25, 2024 at 11:16:09AM -0700, Lucas De Marchi wrote: >> Contrary to i915, in xe ADL-N is kept as a different platform, not a >> subplatform of ADL-P. Since the display side doesn't need to >> differentiate between P and N, i.e. IS_ALDERLAKE_P_N() is never called, >> just fixup the compat header to check for both P and N. >> >> Moving ADL-N to be a subplatform would be more complex as the firmware >> loading in xe only handles platforms, not subplatforms, as going forward >> the direction is to check on IP version rather than >> platforms/subplatforms. >> >> Fix warning when initializing display: >> >> xe 0000:00:02.0: [drm:intel_pch_type [xe]] Found Alder Lake PCH >> ------------[ cut here ]------------ >> xe 0000:00:02.0: drm_WARN_ON(!((dev_priv)->info.platform == XE_ALDERLAKE_S) && !((dev_priv)->info.platform == XE_ALDERLAKE_P)) >> >> And wrong paths being taken on the display side. >> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > >ADL-N uses exactly the same display IP as ADL-P (unlike on the GT side >where they differ), so > >Reviewed-by: Matt Roper <matthew.d.roper@intel.com> applied, thanks Lucas De Marchi
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index ffaa4d2f1eed..cd4632276141 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -78,7 +78,8 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_ROCKETLAKE) #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, XE_DG1) #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_S) -#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_P) +#define IS_ALDERLAKE_P(dev_priv) (IS_PLATFORM(dev_priv, XE_ALDERLAKE_P) || \ + IS_PLATFORM(dev_priv, XE_ALDERLAKE_N)) #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2) #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE) #define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
Contrary to i915, in xe ADL-N is kept as a different platform, not a subplatform of ADL-P. Since the display side doesn't need to differentiate between P and N, i.e. IS_ALDERLAKE_P_N() is never called, just fixup the compat header to check for both P and N. Moving ADL-N to be a subplatform would be more complex as the firmware loading in xe only handles platforms, not subplatforms, as going forward the direction is to check on IP version rather than platforms/subplatforms. Fix warning when initializing display: xe 0000:00:02.0: [drm:intel_pch_type [xe]] Found Alder Lake PCH ------------[ cut here ]------------ xe 0000:00:02.0: drm_WARN_ON(!((dev_priv)->info.platform == XE_ALDERLAKE_S) && !((dev_priv)->info.platform == XE_ALDERLAKE_P)) And wrong paths being taken on the display side. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)