Message ID | 1342277833-3694-1-git-send-email-przanoni@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Sat, Jul 14, 2012 at 11:57:12AM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni <paulo.r.zanoni@intel.com> > > When we enable/disable the CPU backlight registers we can't forget to > enable/disable the PCH backlight registers. Since we're using the CPU > registers we should also unset the override bit. > > Fixes a regression on the following commit: > drm/i915: properly enable the blc controller on the right pipe > > The commit just deleted the code that sets the PCH registers, so it > was relying on the values set by the BIOS. I told my BIOS to boot on > the DVI monitor instead of the LVDS panel, so I noticed the bug. > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Ok, I've double-check bspec, and at least on ilk, snb & ivb this seems to be a sane thing to do. Patch queued for -next, thanks. -Daniel
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 58c7ee7..10c7d39 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -289,11 +289,17 @@ void intel_panel_disable_backlight(struct drm_device *dev) intel_panel_actually_set_backlight(dev, 0); if (INTEL_INFO(dev)->gen >= 4) { - uint32_t reg; + uint32_t reg, tmp; reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2; I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE); + + if (HAS_PCH_SPLIT(dev)) { + tmp = I915_READ(BLC_PWM_PCH_CTL1); + tmp &= ~BLM_PCH_PWM_ENABLE; + I915_WRITE(BLC_PWM_PCH_CTL1, tmp); + } } } @@ -333,6 +339,13 @@ void intel_panel_enable_backlight(struct drm_device *dev, I915_WRITE(reg, tmp); POSTING_READ(reg); I915_WRITE(reg, tmp | BLM_PWM_ENABLE); + + if (HAS_PCH_SPLIT(dev)) { + tmp = I915_READ(BLC_PWM_PCH_CTL1); + tmp |= BLM_PCH_PWM_ENABLE; + tmp &= ~BLM_PCH_OVERRIDE_ENABLE; + I915_WRITE(BLC_PWM_PCH_CTL1, tmp); + } } }