| Message ID | 20240610-crux-unloaded-93b701646454@wendy (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | PolarFire SoC Icicle Reference Design PCIe ?support?/fixes | expand |
Conor Dooley wrote: > On PolarFire SoC the PCIe root port is limited to 32-bit addressing > (both when acting as an AXI-Slave and as an AXI-Master) due to how it > is connected to the processor core complex via a Fabric Interface > Controller (FIC), rather than being part of the Microprocessor Subsystem > (MSS) like the other hard peripherals. > The AXI buses between the FIC and the MSS are true 64-bit buses, but the > PCIe root port is (effectively) only attached to the lower 32-bits of > each bus. As PolarFire SoC is an FPGA, several of Microchip's customers > that did not want to suffer the penalty of bounce buffering inserted a > "shim" in the FPGA fabric that would alter the address of the AXI-S > transaction on the return path to the MSS (conceptually moving the 4GiB > range that the root port can address via the AXI-S interface around > 64-bit space to better cover where those customers had placed their > DDR). PolarFire SoC has a memory map with various apertures into the > physical DDR, and depending on the MSS' configuration, the FPGA design > can control what physical memory addresses back each aperture. > > The main apertures, which are cached memory, lie at 0x10_0000_0000 and > 0x8000_0000. There are also non-cached apertures at 0xC000_0000 and > 0x14_0000_0000. The "default" configuration is to have each of apertures > overlap. > > Some use-cases add a shim to the FPGA fabric that will re-route > transactions from the 0x10_0000_0000 region to avoid bounce buffering > for 64-bit addresses or because the aperture at 0x8000_0000 does not > correspond to usable memory (perhaps an AMP context is using it or the > designer chose not to place memory at the aperture's physical address). > Other user-cases re-route them to the non-cached region at > 0x14_0000_0000. If the latter is done, > DMA for the PCIe root ports become non-coherent. Such a scheme is only > possible because the SiFive ccache on PolarFire SoC can perform flush > invalidation of the L1/L2 cache for these types of configuration. > > Add an Erratum to support this second type of configuration. Like the JH7100's > non-coherent DMA option, this requires use of DMA_GLOBAL_POOL and is > therefore incompatible with Zicbom. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > --- > arch/riscv/Kconfig.errata | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata > index 2acc7d876e1fb..0a9e13efbe6b5 100644 > --- a/arch/riscv/Kconfig.errata > +++ b/arch/riscv/Kconfig.errata > @@ -21,6 +21,25 @@ config ERRATA_ANDES_CMO > > If you don't know what to do here, say "Y". > > +config ERRATA_MICROCHIP > + bool "Microchip errata" > + depends on ARCH_MICROCHIP > + help > + All Microchip errata Kconfig options depend on this option. Disabling > + this option will disable all Microchip errata. > + > +config ERRATA_POLARFIRE_SOC_DMA_NON_COHERENT > + bool "Non-coherent DMA support for PolarFire SoC" > + depends on NONPORTABLE > + depends on ERRATA_MICROCHIP > + select DMA_GLOBAL_POOL > + select RISCV_NONSTANDARD_CACHE_OPS > + help > + Enable support for non-coherent DMA on PolarFire SoC. > + This support is not required for any peripherals in the MSS, but may > + be required for peripherals in the FPGA fabric and is required for > + the PCI root port to operate correctly, due to addressing limitations. > + > config ERRATA_SIFIVE > bool "SiFive errata" > depends on RISCV_ALTERNATIVE > -- > 2.43.2 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 2acc7d876e1fb..0a9e13efbe6b5 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -21,6 +21,25 @@ config ERRATA_ANDES_CMO If you don't know what to do here, say "Y". +config ERRATA_MICROCHIP + bool "Microchip errata" + depends on ARCH_MICROCHIP + help + All Microchip errata Kconfig options depend on this option. Disabling + this option will disable all Microchip errata. + +config ERRATA_POLARFIRE_SOC_DMA_NON_COHERENT + bool "Non-coherent DMA support for PolarFire SoC" + depends on NONPORTABLE + depends on ERRATA_MICROCHIP + select DMA_GLOBAL_POOL + select RISCV_NONSTANDARD_CACHE_OPS + help + Enable support for non-coherent DMA on PolarFire SoC. + This support is not required for any peripherals in the MSS, but may + be required for peripherals in the FPGA fabric and is required for + the PCI root port to operate correctly, due to addressing limitations. + config ERRATA_SIFIVE bool "SiFive errata" depends on RISCV_ALTERNATIVE
On PolarFire SoC the PCIe root port is limited to 32-bit addressing (both when acting as an AXI-Slave and as an AXI-Master) due to how it is connected to the processor core complex via a Fabric Interface Controller (FIC), rather than being part of the Microprocessor Subsystem (MSS) like the other hard peripherals. The AXI buses between the FIC and the MSS are true 64-bit buses, but the PCIe root port is (effectively) only attached to the lower 32-bits of each bus. As PolarFire SoC is an FPGA, several of Microchip's customers that did not want to suffer the penalty of bounce buffering inserted a "shim" in the FPGA fabric that would alter the address of the AXI-S transaction on the return path to the MSS (conceptually moving the 4GiB range that the root port can address via the AXI-S interface around 64-bit space to better cover where those customers had placed their DDR). PolarFire SoC has a memory map with various apertures into the physical DDR, and depending on the MSS' configuration, the FPGA design can control what physical memory addresses back each aperture. The main apertures, which are cached memory, lie at 0x10_0000_0000 and 0x8000_0000. There are also non-cached apertures at 0xC000_0000 and 0x14_0000_0000. The "default" configuration is to have each of apertures overlap. Some use-cases add a shim to the FPGA fabric that will re-route transactions from the 0x10_0000_0000 region to avoid bounce buffering for 64-bit addresses or because the aperture at 0x8000_0000 does not correspond to usable memory (perhaps an AMP context is using it or the designer chose not to place memory at the aperture's physical address). Other user-cases re-route them to the non-cached region at 0x14_0000_0000. If the latter is done, DMA for the PCIe root ports become non-coherent. Such a scheme is only possible because the SiFive ccache on PolarFire SoC can perform flush invalidation of the L1/L2 cache for these types of configuration. Add an Erratum to support this second type of configuration. Like the JH7100's non-coherent DMA option, this requires use of DMA_GLOBAL_POOL and is therefore incompatible with Zicbom. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- arch/riscv/Kconfig.errata | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)