| Message ID | 20240624104239.132159-3-thippesw@amd.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | Add support for Xilinx XDMA Soft IP as Root Port | expand |
Hi Thippeswamy, kernel test robot noticed the following build warnings: [auto build test WARNING on pci/next] [also build test WARNING on pci/for-linus linus/master v6.10-rc5 next-20240625] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Thippeswamy-Havalige/dt-bindings-PCI-xilinx-xdma-Add-schemas-for-Xilinx-QDMA-PCIe-Root-Port-Bridge/20240626-052852 base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next patch link: https://lore.kernel.org/r/20240624104239.132159-3-thippesw%40amd.com patch subject: [PATCH 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver config: loongarch-allyesconfig (https://download.01.org/0day-ci/archive/20240627/202406270344.9nOuTH5k-lkp@intel.com/config) compiler: loongarch64-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240627/202406270344.9nOuTH5k-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406270344.9nOuTH5k-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/pci/controller/pcie-xilinx-dma-pl.c:130: warning: Function parameter or struct member 'cfg_base' not described in 'pl_dma_pcie' >> drivers/pci/controller/pcie-xilinx-dma-pl.c:130: warning: Function parameter or struct member 'variant' not described in 'pl_dma_pcie' vim +130 drivers/pci/controller/pcie-xilinx-dma-pl.c 8d786149d78c77 Thippeswamy Havalige 2023-10-03 101 8d786149d78c77 Thippeswamy Havalige 2023-10-03 102 /** 8d786149d78c77 Thippeswamy Havalige 2023-10-03 103 * struct pl_dma_pcie - PCIe port information 8d786149d78c77 Thippeswamy Havalige 2023-10-03 104 * @dev: Device pointer 8d786149d78c77 Thippeswamy Havalige 2023-10-03 105 * @reg_base: IO Mapped Register Base 8d786149d78c77 Thippeswamy Havalige 2023-10-03 106 * @irq: Interrupt number 8d786149d78c77 Thippeswamy Havalige 2023-10-03 107 * @cfg: Holds mappings of config space window 8d786149d78c77 Thippeswamy Havalige 2023-10-03 108 * @phys_reg_base: Physical address of reg base 8d786149d78c77 Thippeswamy Havalige 2023-10-03 109 * @intx_domain: Legacy IRQ domain pointer 8d786149d78c77 Thippeswamy Havalige 2023-10-03 110 * @pldma_domain: PL DMA IRQ domain pointer 8d786149d78c77 Thippeswamy Havalige 2023-10-03 111 * @resources: Bus Resources 8d786149d78c77 Thippeswamy Havalige 2023-10-03 112 * @msi: MSI information 8d786149d78c77 Thippeswamy Havalige 2023-10-03 113 * @intx_irq: INTx error interrupt number 8d786149d78c77 Thippeswamy Havalige 2023-10-03 114 * @lock: Lock protecting shared register access 8d786149d78c77 Thippeswamy Havalige 2023-10-03 115 */ 8d786149d78c77 Thippeswamy Havalige 2023-10-03 116 struct pl_dma_pcie { 8d786149d78c77 Thippeswamy Havalige 2023-10-03 117 struct device *dev; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 118 void __iomem *reg_base; 21ff31dc400101 Thippeswamy Havalige 2024-06-24 119 void __iomem *cfg_base; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 120 int irq; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 121 struct pci_config_window *cfg; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 122 phys_addr_t phys_reg_base; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 123 struct irq_domain *intx_domain; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 124 struct irq_domain *pldma_domain; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 125 struct list_head resources; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 126 struct xilinx_msi msi; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 127 int intx_irq; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 128 raw_spinlock_t lock; 21ff31dc400101 Thippeswamy Havalige 2024-06-24 129 const struct xilinx_pl_dma_variant *variant; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 @130 }; 8d786149d78c77 Thippeswamy Havalige 2023-10-03 131
diff --git a/drivers/pci/controller/pcie-xilinx-dma-pl.c b/drivers/pci/controller/pcie-xilinx-dma-pl.c index 5be5dfd..11ba656 100644 --- a/drivers/pci/controller/pcie-xilinx-dma-pl.c +++ b/drivers/pci/controller/pcie-xilinx-dma-pl.c @@ -13,6 +13,7 @@ #include <linux/msi.h> #include <linux/of_address.h> #include <linux/of_pci.h> +#include <linux/of_platform.h> #include "../pci.h" #include "pcie-xilinx-common.h" @@ -71,10 +72,24 @@ /* Phy Status/Control Register definitions */ #define XILINX_PCIE_DMA_REG_PSCR_LNKUP BIT(11) +#define QDMA_BRIDGE_BASE_OFF 0xCD8 /* Number of MSI IRQs */ #define XILINX_NUM_MSI_IRQS 64 +enum xilinx_pl_dma_version { + XDMA, + QDMA, +}; + +/** + * struct xilinx_pl_dma_variant - CPM variant information + * @version: DMA version + */ +struct xilinx_pl_dma_variant { + enum xilinx_pl_dma_version version; +}; + struct xilinx_msi { struct irq_domain *msi_domain; unsigned long *bitmap; @@ -101,6 +116,7 @@ struct xilinx_msi { struct pl_dma_pcie { struct device *dev; void __iomem *reg_base; + void __iomem *cfg_base; int irq; struct pci_config_window *cfg; phys_addr_t phys_reg_base; @@ -110,16 +126,23 @@ struct pl_dma_pcie { struct xilinx_msi msi; int intx_irq; raw_spinlock_t lock; + const struct xilinx_pl_dma_variant *variant; }; static inline u32 pcie_read(struct pl_dma_pcie *port, u32 reg) { - return readl(port->reg_base + reg); + if (port->variant->version == XDMA) + return readl(port->reg_base + reg); + else + return readl(port->reg_base + reg + QDMA_BRIDGE_BASE_OFF); } static inline void pcie_write(struct pl_dma_pcie *port, u32 val, u32 reg) { - writel(val, port->reg_base + reg); + if (port->variant->version == XDMA) + writel(val, port->reg_base + reg); + else + writel(val, port->reg_base + reg + QDMA_BRIDGE_BASE_OFF); } static inline bool xilinx_pl_dma_pcie_link_up(struct pl_dma_pcie *port) @@ -173,7 +196,10 @@ static void __iomem *xilinx_pl_dma_pcie_map_bus(struct pci_bus *bus, if (!xilinx_pl_dma_pcie_valid_device(bus, devfn)) return NULL; - return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); + if (port->variant->version == XDMA) + return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); + else + return port->cfg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); } /* PCIe operations */ @@ -731,6 +757,15 @@ static int xilinx_pl_dma_pcie_parse_dt(struct pl_dma_pcie *port, port->reg_base = port->cfg->win; + if (port->variant->version == QDMA) { + port->cfg_base = port->cfg->win; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg"); + port->reg_base = devm_ioremap_resource(dev, res); + if (IS_ERR(port->reg_base)) + return PTR_ERR(port->reg_base); + port->phys_reg_base = res->start; + } + err = xilinx_request_msi_irq(port); if (err) { pci_ecam_free(port->cfg); @@ -760,6 +795,8 @@ static int xilinx_pl_dma_pcie_probe(struct platform_device *pdev) if (!bus) return -ENODEV; + port->variant = of_device_get_match_data(dev); + err = xilinx_pl_dma_pcie_parse_dt(port, bus->res); if (err) { dev_err(dev, "Parsing DT failed\n"); @@ -791,9 +828,22 @@ static int xilinx_pl_dma_pcie_probe(struct platform_device *pdev) return err; } +static const struct xilinx_pl_dma_variant xdma_host = { + .version = XDMA, +}; + +static const struct xilinx_pl_dma_variant qdma_host = { + .version = QDMA, +}; + static const struct of_device_id xilinx_pl_dma_pcie_of_match[] = { { .compatible = "xlnx,xdma-host-3.00", + .data = &xdma_host, + }, + { + .compatible = "xlnx,qdma-host-3.00", + .data = &qdma_host, }, {} };
Add support for Xilinx QDMA Soft IP core as Root Port. The versal prime devices support QDMA soft IP module in programmable logic. The integrated QDMA Soft IP block has integrated bridge function that can act as PCIe Root Port. Signed-off-by: Thippeswamy Havalige <thippesw@amd.com> --- drivers/pci/controller/pcie-xilinx-dma-pl.c | 56 +++++++++++++++++++++++++++-- 1 file changed, 53 insertions(+), 3 deletions(-)