| Message ID | 20240709-add_qcs9100_pcie_ep_compatible-v2-2-217742eac32b@quicinc.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | PCI: qcom-ep: Add QCS9100 PCIe ep compatible | expand |
On Tue, Jul 09, 2024 at 10:53:44PM +0800, Tengfei Fan wrote: > QCS9100 SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP, > so add support for it by passing the mapping format and the number of > read/write channels count. > > The PCIe EP controller used on this SoC is of version 1.34.0, so a separate > config struct is introduced for the sake of enabling HDMA conditionally. This patch doesn't add a new config struct. > It should be noted that for the eDMA support (predecessor of HDMA), there > are no mapping format and channels count specified. That is because eDMA > supports auto detection of both parameters, whereas HDMA doesn't. > > QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p > platform use non-SCMI resource. In the future, the SA8775p platform will > move to use SCMI resources and it will have new sa8775p-related device > tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to the PCIe device > match table. This series doesn't add the new SCMI stuff you mention. It sounds like this should be deferred and added when you actually move to using SCMI resources. > Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> > --- > drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c > index 236229f66c80..e2775f4ca7ee 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c > +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c > @@ -904,6 +904,7 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { > }; > > static const struct of_device_id qcom_pcie_ep_match[] = { > + { .compatible = "qcom,qcs9100-pcie-ep", .data = &cfg_1_34_0}, > { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, > { .compatible = "qcom,sdx55-pcie-ep", }, > { .compatible = "qcom,sm8450-pcie-ep", }, > > -- > 2.25.1 >
On 7/10/2024 12:26 AM, Bjorn Helgaas wrote: > On Tue, Jul 09, 2024 at 10:53:44PM +0800, Tengfei Fan wrote: >> QCS9100 SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP, >> so add support for it by passing the mapping format and the number of >> read/write channels count. >> >> The PCIe EP controller used on this SoC is of version 1.34.0, so a separate >> config struct is introduced for the sake of enabling HDMA conditionally. > > This patch doesn't add a new config struct. Thank you for pointing out this. I will remove this commit message in the next version patch series. > >> It should be noted that for the eDMA support (predecessor of HDMA), there >> are no mapping format and channels count specified. That is because eDMA >> supports auto detection of both parameters, whereas HDMA doesn't. >> >> QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p >> platform use non-SCMI resource. In the future, the SA8775p platform will >> move to use SCMI resources and it will have new sa8775p-related device >> tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to the PCIe device >> match table. > > This series doesn't add the new SCMI stuff you mention. It sounds > like this should be deferred and added when you actually move to using > SCMI resources. This patch shouldn't be deferred. This patch is used to support QSC9100. QCS9100 uses non-SCMI resources, so there is nothing related to SCMI in this patch. Only SA8775p will move to use SCMI resources in the future. > >> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> >> --- >> drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c >> index 236229f66c80..e2775f4ca7ee 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c >> @@ -904,6 +904,7 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { >> }; >> >> static const struct of_device_id qcom_pcie_ep_match[] = { >> + { .compatible = "qcom,qcs9100-pcie-ep", .data = &cfg_1_34_0}, >> { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, >> { .compatible = "qcom,sdx55-pcie-ep", }, >> { .compatible = "qcom,sm8450-pcie-ep", }, >> >> -- >> 2.25.1 >>
On 7/10/2024 12:26 AM, Bjorn Helgaas wrote: > On Tue, Jul 09, 2024 at 10:53:44PM +0800, Tengfei Fan wrote: >> QCS9100 SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP, >> so add support for it by passing the mapping format and the number of >> read/write channels count. >> >> The PCIe EP controller used on this SoC is of version 1.34.0, so a separate >> config struct is introduced for the sake of enabling HDMA conditionally. > > This patch doesn't add a new config struct. > >> It should be noted that for the eDMA support (predecessor of HDMA), there >> are no mapping format and channels count specified. That is because eDMA >> supports auto detection of both parameters, whereas HDMA doesn't. >> >> QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p >> platform use non-SCMI resource. In the future, the SA8775p platform will >> move to use SCMI resources and it will have new sa8775p-related device >> tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to the PCIe device >> match table. > > This series doesn't add the new SCMI stuff you mention. It sounds > like this should be deferred and added when you actually move to using > SCMI resources. We can rename "sa8775p" to "qcs9100" compatible name in next patchset for this driver. Let's know if this is reasonable from your point of view? SCMI resource solution will come in a later point, and at that time it can have scmi related resource operations in this driver and add "sa8775p" compatible with correct resources ops at that time. More background: We want to make QCS9100 non-SCMI resources not blocking by current SCMI resources changes, since SCMI changes are also pending to merge in order to not blocking non-scmi resource platforms like current QCS9100 project. So the splitting base device trees are pending here. Don't want to have a circular dependency loop. :) > >> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> >> --- >> drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c >> index 236229f66c80..e2775f4ca7ee 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c >> @@ -904,6 +904,7 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { >> }; >> >> static const struct of_device_id qcom_pcie_ep_match[] = { >> + { .compatible = "qcom,qcs9100-pcie-ep", .data = &cfg_1_34_0}, >> { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, >> { .compatible = "qcom,sdx55-pcie-ep", }, >> { .compatible = "qcom,sm8450-pcie-ep", }, >> >> -- >> 2.25.1 >>
On 7/10/2024 6:40 PM, Aiqun Yu (Maria) wrote: > > > On 7/10/2024 12:26 AM, Bjorn Helgaas wrote: >> On Tue, Jul 09, 2024 at 10:53:44PM +0800, Tengfei Fan wrote: >>> QCS9100 SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP, >>> so add support for it by passing the mapping format and the number of >>> read/write channels count. >>> >>> The PCIe EP controller used on this SoC is of version 1.34.0, so a separate >>> config struct is introduced for the sake of enabling HDMA conditionally. >> >> This patch doesn't add a new config struct. >> >>> It should be noted that for the eDMA support (predecessor of HDMA), there >>> are no mapping format and channels count specified. That is because eDMA >>> supports auto detection of both parameters, whereas HDMA doesn't. >>> >>> QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p >>> platform use non-SCMI resource. In the future, the SA8775p platform will >>> move to use SCMI resources and it will have new sa8775p-related device >>> tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to the PCIe device >>> match table. >> >> This series doesn't add the new SCMI stuff you mention. It sounds >> like this should be deferred and added when you actually move to using >> SCMI resources. > > We can rename "sa8775p" to "qcs9100" compatible name in next patchset > for this driver. Let's know if this is reasonable from your point of view? > > SCMI resource solution will come in a later point, and at that time it > can have scmi related resource operations in this driver and add > "sa8775p" compatible with correct resources ops at that time. > > More background: > We want to make QCS9100 non-SCMI resources not blocking by current SCMI > resources changes, since SCMI changes are also pending to merge in order > to not blocking non-scmi resource platforms like current QCS9100 > project. So the splitting base device trees are pending here. Don't want > to have a circular dependency loop. :) After considering the feedback provided on the subject, We have decided to keep current SA8775p compatible and ABI compatibility in drivers. Let's close this session and ignore all the current patches here. Thank you for your input. >> >>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> >>> --- >>> drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c >>> index 236229f66c80..e2775f4ca7ee 100644 >>> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c >>> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c >>> @@ -904,6 +904,7 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { >>> }; >>> >>> static const struct of_device_id qcom_pcie_ep_match[] = { >>> + { .compatible = "qcom,qcs9100-pcie-ep", .data = &cfg_1_34_0}, >>> { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, >>> { .compatible = "qcom,sdx55-pcie-ep", }, >>> { .compatible = "qcom,sm8450-pcie-ep", }, >>> >>> -- >>> 2.25.1 >>> >
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 236229f66c80..e2775f4ca7ee 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -904,6 +904,7 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { }; static const struct of_device_id qcom_pcie_ep_match[] = { + { .compatible = "qcom,qcs9100-pcie-ep", .data = &cfg_1_34_0}, { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, { .compatible = "qcom,sdx55-pcie-ep", }, { .compatible = "qcom,sm8450-pcie-ep", },
QCS9100 SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP, so add support for it by passing the mapping format and the number of read/write channels count. The PCIe EP controller used on this SoC is of version 1.34.0, so a separate config struct is introduced for the sake of enabling HDMA conditionally. It should be noted that for the eDMA support (predecessor of HDMA), there are no mapping format and channels count specified. That is because eDMA supports auto detection of both parameters, whereas HDMA doesn't. QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p platform use non-SCMI resource. In the future, the SA8775p platform will move to use SCMI resources and it will have new sa8775p-related device tree. Consequently, introduce "qcom,qcs9100-pcie-ep" to the PCIe device match table. Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+)