| Message ID | 20240719115018.27356-1-eric.lin@sifive.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 63ba5b0fb4f54db256ec43b3062b2606b383055d |
| Headers | show |
| Series | [v2] perf arch events: Fix duplicate RISC-V SBI firmware event name | expand |
On Fri, Jul 19, 2024 at 07:50:18PM GMT, Eric Lin wrote: > Currently, the RISC-V firmware JSON file has duplicate event name > "FW_SFENCE_VMA_RECEIVED". According to the RISC-V SBI PMU extension[1], > the event name should be "FW_SFENCE_VMA_ASID_SENT". > > Before this patch: > $ perf list > > firmware: > fw_access_load > [Load access trap event. Unit: cpu] > fw_access_store > [Store access trap event. Unit: cpu] > .... > fw_set_timer > [Set timer event. Unit: cpu] > fw_sfence_vma_asid_received > [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] > fw_sfence_vma_received > [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu] > > After this patch: > $ perf list > > firmware: > fw_access_load > [Load access trap event. Unit: cpu] > fw_access_store > [Store access trap event. Unit: cpu] > ..... > fw_set_timer > [Set timer event. Unit: cpu] > fw_sfence_vma_asid_received > [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] > fw_sfence_vma_asid_sent > [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu] > fw_sfence_vma_received > [Received SFENCE.VMA request from other HART event. Unit: cpu] > > Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-pmu.adoc#event-firmware-events-type-15 [1] > Fixes: 8f0dcb4e7364 ("perf arch events: riscv sbi firmware std event files") > Fixes: c4f769d4093d ("perf vendor events riscv: add Sifive U74 JSON file") > Fixes: acbf6de674ef ("perf vendor events riscv: Add StarFive Dubhe-80 JSON file") > Fixes: 7340c6df49df ("perf vendor events riscv: add T-HEAD C9xx JSON file") > Fixes: f5102e31c209 ("riscv: andes: Support specifying symbolic firmware and hardware raw event") > Signed-off-by: Eric Lin <eric.lin@sifive.com> > Reviewed-by: Samuel Holland <samuel.holland@sifive.com> > Reviewed-by: Nikita Shubin <n.shubin@yadro.com> > --- Thanks for the fix. Reviewed-by: Inochi Amaoto <inochiama@outlook.com> > Changes since V1: > - Add "Fixes:" tag for every patch that copied firmware.json > --- > tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json | 2 +- > tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json | 2 +- > tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json | 2 +- > .../perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json | 2 +- > .../perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json | 2 +- > 5 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > diff --git a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json > index a9939823b14b..0c9b9a2d2958 100644 > --- a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json > @@ -74,7 +74,7 @@ > { > "PublicDescription": "Sent SFENCE.VMA with ASID request to other HART event", > "ConfigCode": "0x800000000000000c", > - "EventName": "FW_SFENCE_VMA_RECEIVED", > + "EventName": "FW_SFENCE_VMA_ASID_SENT", > "BriefDescription": "Sent SFENCE.VMA with ASID request to other HART event" > }, > { > diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > diff --git a/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json b/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > diff --git a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > -- > 2.43.2 >
On Fri, Jul 19, 2024 at 07:50:18PM GMT, Eric Lin wrote: > Currently, the RISC-V firmware JSON file has duplicate event name > "FW_SFENCE_VMA_RECEIVED". According to the RISC-V SBI PMU extension[1], > the event name should be "FW_SFENCE_VMA_ASID_SENT". > > Before this patch: > $ perf list > > firmware: > fw_access_load > [Load access trap event. Unit: cpu] > fw_access_store > [Store access trap event. Unit: cpu] > .... > fw_set_timer > [Set timer event. Unit: cpu] > fw_sfence_vma_asid_received > [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] > fw_sfence_vma_received > [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu] > > After this patch: > $ perf list > > firmware: > fw_access_load > [Load access trap event. Unit: cpu] > fw_access_store > [Store access trap event. Unit: cpu] > ..... > fw_set_timer > [Set timer event. Unit: cpu] > fw_sfence_vma_asid_received > [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] > fw_sfence_vma_asid_sent > [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu] > fw_sfence_vma_received > [Received SFENCE.VMA request from other HART event. Unit: cpu] > > Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-pmu.adoc#event-firmware-events-type-15 [1] > Fixes: 8f0dcb4e7364 ("perf arch events: riscv sbi firmware std event files") > Fixes: c4f769d4093d ("perf vendor events riscv: add Sifive U74 JSON file") > Fixes: acbf6de674ef ("perf vendor events riscv: Add StarFive Dubhe-80 JSON file") > Fixes: 7340c6df49df ("perf vendor events riscv: add T-HEAD C9xx JSON file") > Fixes: f5102e31c209 ("riscv: andes: Support specifying symbolic firmware and hardware raw event") > Signed-off-by: Eric Lin <eric.lin@sifive.com> > Reviewed-by: Samuel Holland <samuel.holland@sifive.com> > Reviewed-by: Nikita Shubin <n.shubin@yadro.com> > --- > Changes since V1: > - Add "Fixes:" tag for every patch that copied firmware.json > --- > tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json | 2 +- > tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json | 2 +- > tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json | 2 +- > .../perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json | 2 +- > .../perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json | 2 +- > 5 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > diff --git a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json > index a9939823b14b..0c9b9a2d2958 100644 > --- a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json > @@ -74,7 +74,7 @@ > { > "PublicDescription": "Sent SFENCE.VMA with ASID request to other HART event", > "ConfigCode": "0x800000000000000c", > - "EventName": "FW_SFENCE_VMA_RECEIVED", > + "EventName": "FW_SFENCE_VMA_ASID_SENT", > "BriefDescription": "Sent SFENCE.VMA with ASID request to other HART event" > }, > { > diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > diff --git a/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json b/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > diff --git a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > -- > 2.43.2 > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Currently, the RISC-V firmware JSON file has duplicate event name > "FW_SFENCE_VMA_RECEIVED". According to the RISC-V SBI PMU extension[1], > the event name should be "FW_SFENCE_VMA_ASID_SENT". > > Before this patch: > $ perf list > > firmware: > fw_access_load > [Load access trap event. Unit: cpu] > fw_access_store > [Store access trap event. Unit: cpu] > .... > fw_set_timer > [Set timer event. Unit: cpu] > fw_sfence_vma_asid_received > [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] > fw_sfence_vma_received > [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu] > > After this patch: > $ perf list > > firmware: > fw_access_load > [Load access trap event. Unit: cpu] > fw_access_store > [Store access trap event. Unit: cpu] > ..... > fw_set_timer > [Set timer event. Unit: cpu] > fw_sfence_vma_asid_received > [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] > fw_sfence_vma_asid_sent > [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu] > fw_sfence_vma_received > [Received SFENCE.VMA request from other HART event. Unit: cpu] > > Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-pmu.adoc#event-firmware-events-type-15 [1] > Fixes: 8f0dcb4e7364 ("perf arch events: riscv sbi firmware std event files") > Fixes: c4f769d4093d ("perf vendor events riscv: add Sifive U74 JSON file") > Fixes: acbf6de674ef ("perf vendor events riscv: Add StarFive Dubhe-80 JSON file") > Fixes: 7340c6df49df ("perf vendor events riscv: add T-HEAD C9xx JSON file") > Fixes: f5102e31c209 ("riscv: andes: Support specifying symbolic firmware and hardware raw event") > Signed-off-by: Eric Lin <eric.lin@sifive.com> > Reviewed-by: Samuel Holland <samuel.holland@sifive.com> > Reviewed-by: Nikita Shubin <n.shubin@yadro.com> > --- > Changes since V1: > - Add "Fixes:" tag for every patch that copied firmware.json > --- > tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json | 2 +- > tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json | 2 +- > tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json | 2 +- > .../perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json | 2 +- > .../perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json | 2 +- > 5 files changed, 5 insertions(+), 5 deletions(-) > diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > diff --git a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json > index a9939823b14b..0c9b9a2d2958 100644 > --- a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json > @@ -74,7 +74,7 @@ > { > "PublicDescription": "Sent SFENCE.VMA with ASID request to other HART event", > "ConfigCode": "0x800000000000000c", > - "EventName": "FW_SFENCE_VMA_RECEIVED", > + "EventName": "FW_SFENCE_VMA_ASID_SENT", > "BriefDescription": "Sent SFENCE.VMA with ASID request to other HART event" > }, > { > diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > diff --git a/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json b/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > diff --git a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" >
> Currently, the RISC-V firmware JSON file has duplicate event name > "FW_SFENCE_VMA_RECEIVED". According to the RISC-V SBI PMU extension[1], > the event name should be "FW_SFENCE_VMA_ASID_SENT". > > Before this patch: > $ perf list > > firmware: > fw_access_load > [Load access trap event. Unit: cpu] > fw_access_store > [Store access trap event. Unit: cpu] > .... > fw_set_timer > [Set timer event. Unit: cpu] > fw_sfence_vma_asid_received > [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] > fw_sfence_vma_received > [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu] > > After this patch: > $ perf list > > firmware: > fw_access_load > [Load access trap event. Unit: cpu] > fw_access_store > [Store access trap event. Unit: cpu] > ..... > fw_set_timer > [Set timer event. Unit: cpu] > fw_sfence_vma_asid_received > [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] > fw_sfence_vma_asid_sent > [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu] > fw_sfence_vma_received > [Received SFENCE.VMA request from other HART event. Unit: cpu] > > Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-pmu.adoc#event-firmware-events-type-15 [1] > Fixes: 8f0dcb4e7364 ("perf arch events: riscv sbi firmware std event files") > Fixes: c4f769d4093d ("perf vendor events riscv: add Sifive U74 JSON file") > Fixes: acbf6de674ef ("perf vendor events riscv: Add StarFive Dubhe-80 JSON file") > Fixes: 7340c6df49df ("perf vendor events riscv: add T-HEAD C9xx JSON file") > Fixes: f5102e31c209 ("riscv: andes: Support specifying symbolic firmware and hardware raw event") > Signed-off-by: Eric Lin <eric.lin@sifive.com> > Reviewed-by: Samuel Holland <samuel.holland@sifive.com> > Reviewed-by: Nikita Shubin <n.shubin@yadro.com> > --- > Changes since V1: > - Add "Fixes:" tag for every patch that copied firmware.json > --- > tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json | 2 +- > tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json | 2 +- > tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json | 2 +- > .../perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json | 2 +- > .../perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json | 2 +- > 5 files changed, 5 insertions(+), 5 deletions(-) > diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > diff --git a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json > index a9939823b14b..0c9b9a2d2958 100644 > --- a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json > @@ -74,7 +74,7 @@ > { > "PublicDescription": "Sent SFENCE.VMA with ASID request to other HART event", > "ConfigCode": "0x800000000000000c", > - "EventName": "FW_SFENCE_VMA_RECEIVED", > + "EventName": "FW_SFENCE_VMA_ASID_SENT", > "BriefDescription": "Sent SFENCE.VMA with ASID request to other HART event" > }, > { > diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > diff --git a/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json b/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > diff --git a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json > index 9b4a032186a7..7149caec4f80 100644 > --- a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json > +++ b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json > @@ -36,7 +36,7 @@ > "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > }, > { > - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" > + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" > }, > { > "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" > Reviewed-by: Atish Patra <atishp@rivosinc.com>
On Mon, Jul 29, 2024 at 11:19 AM Atish Patra <atishp@rivosinc.com> wrote: > > > Currently, the RISC-V firmware JSON file has duplicate event name > > "FW_SFENCE_VMA_RECEIVED". According to the RISC-V SBI PMU extension[1], > > the event name should be "FW_SFENCE_VMA_ASID_SENT". > > > > Before this patch: > > $ perf list > > > > firmware: > > fw_access_load > > [Load access trap event. Unit: cpu] > > fw_access_store > > [Store access trap event. Unit: cpu] > > .... > > fw_set_timer > > [Set timer event. Unit: cpu] > > fw_sfence_vma_asid_received > > [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] > > fw_sfence_vma_received > > [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu] > > > > After this patch: > > $ perf list > > > > firmware: > > fw_access_load > > [Load access trap event. Unit: cpu] > > fw_access_store > > [Store access trap event. Unit: cpu] > > ..... > > fw_set_timer > > [Set timer event. Unit: cpu] > > fw_sfence_vma_asid_received > > [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] > > fw_sfence_vma_asid_sent > > [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu] > > fw_sfence_vma_received > > [Received SFENCE.VMA request from other HART event. Unit: cpu] > > > > Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-pmu.adoc#event-firmware-events-type-15 [1] > > Fixes: 8f0dcb4e7364 ("perf arch events: riscv sbi firmware std event files") > > Fixes: c4f769d4093d ("perf vendor events riscv: add Sifive U74 JSON file") > > Fixes: acbf6de674ef ("perf vendor events riscv: Add StarFive Dubhe-80 JSON file") > > Fixes: 7340c6df49df ("perf vendor events riscv: add T-HEAD C9xx JSON file") > > Fixes: f5102e31c209 ("riscv: andes: Support specifying symbolic firmware and hardware raw event") > > Signed-off-by: Eric Lin <eric.lin@sifive.com> > > Reviewed-by: Samuel Holland <samuel.holland@sifive.com> > > Reviewed-by: Nikita Shubin <n.shubin@yadro.com> > > --- > > Changes since V1: > > - Add "Fixes:" tag for every patch that copied firmware.json > Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Ian Rogers <irogers@google.com> Thanks, Ian
Hello: This patch was applied to riscv/linux.git (fixes) by Palmer Dabbelt <palmer@rivosinc.com>: On Fri, 19 Jul 2024 19:50:18 +0800 you wrote: > Currently, the RISC-V firmware JSON file has duplicate event name > "FW_SFENCE_VMA_RECEIVED". According to the RISC-V SBI PMU extension[1], > the event name should be "FW_SFENCE_VMA_ASID_SENT". > > Before this patch: > $ perf list > > [...] Here is the summary with links: - [v2] perf arch events: Fix duplicate RISC-V SBI firmware event name https://git.kernel.org/riscv/c/63ba5b0fb4f5 You are awesome, thank you!
On Thu, Aug 1, 2024 at 9:40 AM <patchwork-bot+linux-riscv@kernel.org> wrote: > > Hello: > > This patch was applied to riscv/linux.git (fixes) > by Palmer Dabbelt <palmer@rivosinc.com>: > > On Fri, 19 Jul 2024 19:50:18 +0800 you wrote: > > Currently, the RISC-V firmware JSON file has duplicate event name > > "FW_SFENCE_VMA_RECEIVED". According to the RISC-V SBI PMU extension[1], > > the event name should be "FW_SFENCE_VMA_ASID_SENT". > > > > Before this patch: > > $ perf list > > > > [...] > > Here is the summary with links: > - [v2] perf arch events: Fix duplicate RISC-V SBI firmware event name > https://git.kernel.org/riscv/c/63ba5b0fb4f5 > > You are awesome, thank you! Fwiw, as this change is in tools/perf/pmu-events I was expecting it to go through the perf-tools/perf-tools-next tree. Thanks, Ian
diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json index 9b4a032186a7..7149caec4f80 100644 --- a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json @@ -36,7 +36,7 @@ "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" }, { - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" }, { "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" diff --git a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json index a9939823b14b..0c9b9a2d2958 100644 --- a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json +++ b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json @@ -74,7 +74,7 @@ { "PublicDescription": "Sent SFENCE.VMA with ASID request to other HART event", "ConfigCode": "0x800000000000000c", - "EventName": "FW_SFENCE_VMA_RECEIVED", + "EventName": "FW_SFENCE_VMA_ASID_SENT", "BriefDescription": "Sent SFENCE.VMA with ASID request to other HART event" }, { diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json index 9b4a032186a7..7149caec4f80 100644 --- a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json +++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json @@ -36,7 +36,7 @@ "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" }, { - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" }, { "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" diff --git a/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json b/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json index 9b4a032186a7..7149caec4f80 100644 --- a/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json +++ b/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json @@ -36,7 +36,7 @@ "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" }, { - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" }, { "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" diff --git a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json index 9b4a032186a7..7149caec4f80 100644 --- a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json +++ b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json @@ -36,7 +36,7 @@ "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" }, { - "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" + "ArchStdEvent": "FW_SFENCE_VMA_ASID_SENT" }, { "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
Currently, the RISC-V firmware JSON file has duplicate event name "FW_SFENCE_VMA_RECEIVED". According to the RISC-V SBI PMU extension[1], the event name should be "FW_SFENCE_VMA_ASID_SENT". Before this patch: $ perf list firmware: fw_access_load [Load access trap event. Unit: cpu] fw_access_store [Store access trap event. Unit: cpu] .... fw_set_timer [Set timer event. Unit: cpu] fw_sfence_vma_asid_received [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] fw_sfence_vma_received [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu] After this patch: $ perf list firmware: fw_access_load [Load access trap event. Unit: cpu] fw_access_store [Store access trap event. Unit: cpu] ..... fw_set_timer [Set timer event. Unit: cpu] fw_sfence_vma_asid_received [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] fw_sfence_vma_asid_sent [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu] fw_sfence_vma_received [Received SFENCE.VMA request from other HART event. Unit: cpu] Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-pmu.adoc#event-firmware-events-type-15 [1] Fixes: 8f0dcb4e7364 ("perf arch events: riscv sbi firmware std event files") Fixes: c4f769d4093d ("perf vendor events riscv: add Sifive U74 JSON file") Fixes: acbf6de674ef ("perf vendor events riscv: Add StarFive Dubhe-80 JSON file") Fixes: 7340c6df49df ("perf vendor events riscv: add T-HEAD C9xx JSON file") Fixes: f5102e31c209 ("riscv: andes: Support specifying symbolic firmware and hardware raw event") Signed-off-by: Eric Lin <eric.lin@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Nikita Shubin <n.shubin@yadro.com> --- Changes since V1: - Add "Fixes:" tag for every patch that copied firmware.json --- tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json | 2 +- tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json | 2 +- tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json | 2 +- .../perf/pmu-events/arch/riscv/starfive/dubhe-80/firmware.json | 2 +- .../perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-)