| Message ID | 20240817075629.262318-1-mikisabate@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: hwprobe: export Zicntr and Zihpm extensions | expand |
On Sat, Aug 17, 2024 at 3:58 AM Miquel Sabaté Solà <mikisabate@gmail.com> wrote: > > Export Zicntr and Zihpm ISA extensions through the hwprobe syscall. > > Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com> > --- > Documentation/arch/riscv/hwprobe.rst | 6 ++++++ > arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ > arch/riscv/kernel/sys_hwprobe.c | 2 ++ > 3 files changed, 10 insertions(+) > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > index 3db60a0911df..5bb69c985cce 100644 > --- a/Documentation/arch/riscv/hwprobe.rst > +++ b/Documentation/arch/riscv/hwprobe.rst > @@ -188,10 +188,16 @@ The following keys are defined: > manual starting from commit 95cf1f9 ("Add changes requested by Ved > during signoff") > > + * :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0 > + is supported as defined in the RISC-V ISA manual. > + > * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is > supported as defined in the RISC-V ISA manual starting from commit > d8ab5c78c207 ("Zihintpause is ratified"). > > + * :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0 > + is supported as defined in the RISC-V ISA manual. > + > * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is > supported, as defined by version 1.0 of the RISC-V Vector extension manual. > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index b706c8e47b02..098a815b3fd4 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -72,6 +72,8 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_EXT_ZCF (1ULL << 46) > #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) > #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48) > +#define RISCV_HWPROBE_EXT_ZICNTR (1ULL << 49) > +#define RISCV_HWPROBE_EXT_ZIHPM (1ULL << 50) > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > index 8d1b5c35d2a7..30aede1c90ff 100644 > --- a/arch/riscv/kernel/sys_hwprobe.c > +++ b/arch/riscv/kernel/sys_hwprobe.c > @@ -118,6 +118,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > EXT_KEY(ZKSH); > EXT_KEY(ZKT); > EXT_KEY(ZTSO); > + EXT_KEY(ZICNTR); > + EXT_KEY(ZIHPM); Conor, do we care about ordering? Acked-by: Jesse Taube <jesse@rivosinc.com> > > /* > * All the following extensions must depend on the kernel > -- > 2.46.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Mon, Aug 19, 2024 at 01:29:16PM -0400, Jesse Taube wrote: > On Sat, Aug 17, 2024 at 3:58 AM Miquel Sabaté Solà <mikisabate@gmail.com> wrote: > > > > Export Zicntr and Zihpm ISA extensions through the hwprobe syscall. > > > > Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com> > > --- > > Documentation/arch/riscv/hwprobe.rst | 6 ++++++ > > arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ > > arch/riscv/kernel/sys_hwprobe.c | 2 ++ > > 3 files changed, 10 insertions(+) > > > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > > index 3db60a0911df..5bb69c985cce 100644 > > --- a/Documentation/arch/riscv/hwprobe.rst > > +++ b/Documentation/arch/riscv/hwprobe.rst > > @@ -188,10 +188,16 @@ The following keys are defined: > > manual starting from commit 95cf1f9 ("Add changes requested by Ved > > during signoff") > > > > + * :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0 > > + is supported as defined in the RISC-V ISA manual. > > + > > * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is > > supported as defined in the RISC-V ISA manual starting from commit > > d8ab5c78c207 ("Zihintpause is ratified"). > > > > + * :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0 > > + is supported as defined in the RISC-V ISA manual. > > + > > * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is > > supported, as defined by version 1.0 of the RISC-V Vector extension manual. > > > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > > index b706c8e47b02..098a815b3fd4 100644 > > --- a/arch/riscv/include/uapi/asm/hwprobe.h > > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > > @@ -72,6 +72,8 @@ struct riscv_hwprobe { > > #define RISCV_HWPROBE_EXT_ZCF (1ULL << 46) > > #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) > > #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48) > > +#define RISCV_HWPROBE_EXT_ZICNTR (1ULL << 49) > > +#define RISCV_HWPROBE_EXT_ZIHPM (1ULL << 50) > > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) > > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) The sort here, by number, is fine. > > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > > index 8d1b5c35d2a7..30aede1c90ff 100644 > > --- a/arch/riscv/kernel/sys_hwprobe.c > > +++ b/arch/riscv/kernel/sys_hwprobe.c > > @@ -118,6 +118,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > > EXT_KEY(ZKSH); > > EXT_KEY(ZKT); > > EXT_KEY(ZTSO); > > + EXT_KEY(ZICNTR); > > + EXT_KEY(ZIHPM); > > Conor, do we care about ordering? I would rather that they were sorted alphabetically. Adding to the end is nothing but a conflict generator and makes it harder to see what is and what is not in the list. IIRC Palmer applied the patch I sent a few weeks ago that sorted the entries in all of these EXT_KEY() lists.
> On Mon, Aug 19, 2024 at 01:29:16PM -0400, Jesse Taube wrote: >> On Sat, Aug 17, 2024 at 3:58 AM Miquel Sabaté Solà <mikisabate@gmail.com> wrote: >> > >> > Export Zicntr and Zihpm ISA extensions through the hwprobe syscall. >> > >> > Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com> >> > --- >> > Documentation/arch/riscv/hwprobe.rst | 6 ++++++ >> > arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ >> > arch/riscv/kernel/sys_hwprobe.c | 2 ++ >> > 3 files changed, 10 insertions(+) >> > >> > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst >> > index 3db60a0911df..5bb69c985cce 100644 >> > --- a/Documentation/arch/riscv/hwprobe.rst >> > +++ b/Documentation/arch/riscv/hwprobe.rst >> > @@ -188,10 +188,16 @@ The following keys are defined: >> > manual starting from commit 95cf1f9 ("Add changes requested by Ved >> > during signoff") >> > >> > + * :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0 >> > + is supported as defined in the RISC-V ISA manual. >> > + >> > * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is >> > supported as defined in the RISC-V ISA manual starting from commit >> > d8ab5c78c207 ("Zihintpause is ratified"). >> > >> > + * :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0 >> > + is supported as defined in the RISC-V ISA manual. >> > + >> > * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is >> > supported, as defined by version 1.0 of the RISC-V Vector extension manual. >> > >> > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h >> > index b706c8e47b02..098a815b3fd4 100644 >> > --- a/arch/riscv/include/uapi/asm/hwprobe.h >> > +++ b/arch/riscv/include/uapi/asm/hwprobe.h >> > @@ -72,6 +72,8 @@ struct riscv_hwprobe { >> > #define RISCV_HWPROBE_EXT_ZCF (1ULL << 46) >> > #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) >> > #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48) >> > +#define RISCV_HWPROBE_EXT_ZICNTR (1ULL << 49) >> > +#define RISCV_HWPROBE_EXT_ZIHPM (1ULL << 50) >> > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 >> > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) >> > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) > > The sort here, by number, is fine. > >> > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c >> > index 8d1b5c35d2a7..30aede1c90ff 100644 >> > --- a/arch/riscv/kernel/sys_hwprobe.c >> > +++ b/arch/riscv/kernel/sys_hwprobe.c >> > @@ -118,6 +118,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, >> > EXT_KEY(ZKSH); >> > EXT_KEY(ZKT); >> > EXT_KEY(ZTSO); >> > + EXT_KEY(ZICNTR); >> > + EXT_KEY(ZIHPM); >> >> Conor, do we care about ordering? > > I would rather that they were sorted alphabetically. Adding to the end > is nothing but a conflict generator and makes it harder to see what is > and what is not in the list. IIRC Palmer applied the patch I sent a few > weeks ago that sorted the entries in all of these EXT_KEY() lists. Makes a lot of sense. Let me send a new version of the patch with they keys sorted.
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 3db60a0911df..5bb69c985cce 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -188,10 +188,16 @@ The following keys are defined: manual starting from commit 95cf1f9 ("Add changes requested by Ved during signoff") + * :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0 + is supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is supported as defined in the RISC-V ISA manual starting from commit d8ab5c78c207 ("Zihintpause is ratified"). + * :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0 + is supported as defined in the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is supported, as defined by version 1.0 of the RISC-V Vector extension manual. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index b706c8e47b02..098a815b3fd4 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -72,6 +72,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZCF (1ULL << 46) #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48) +#define RISCV_HWPROBE_EXT_ZICNTR (1ULL << 49) +#define RISCV_HWPROBE_EXT_ZIHPM (1ULL << 50) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index 8d1b5c35d2a7..30aede1c90ff 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -118,6 +118,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZKSH); EXT_KEY(ZKT); EXT_KEY(ZTSO); + EXT_KEY(ZICNTR); + EXT_KEY(ZIHPM); /* * All the following extensions must depend on the kernel
Export Zicntr and Zihpm ISA extensions through the hwprobe syscall. Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com> --- Documentation/arch/riscv/hwprobe.rst | 6 ++++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_hwprobe.c | 2 ++ 3 files changed, 10 insertions(+)