| Message ID | 20240825-02-k1-pinctrl-v2-3-ddd38a345d12@gentoo.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: spacemit: add pinctrl support to K1 SoC | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
On Sun, Aug 25, 2024 at 01:10:04PM GMT, Yixun Lan wrote: > Add pinctrl device tree data to SpacemiT's K1 SoC. > > Signed-off-by: Yixun Lan <dlan@gentoo.org> > --- > Note, only minimal device tree data added in this series, > which just try to demonstrate this pinctrl driver, but > more dt data can be added later, in separate patches. > --- > arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 19 +++++++++++++++++++ > arch/riscv/boot/dts/spacemit/k1.dtsi | 5 +++++ > 2 files changed, 24 insertions(+) > > diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi > new file mode 100644 > index 0000000000000..38ccaad1209f5 > --- /dev/null > +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi > @@ -0,0 +1,19 @@ > +// SPDX-License-Identifier: GPL-2.0 OR MIT > +/* > + * Copyright (c) 2024 Yixun Lan <dlan@gentoo.org> > + */ > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/pinctrl/spacemit,k1-pinctrl.h> > + > +&pinctrl { > + uart0_2_cfg: uart0-2-cfg { > + uart0-2-pins { > + pinmux = <K1_PADCONF(GPIO_68, 2)>, > + <K1_PADCONF(GPIO_69, 2)>; > + > + bias-pull-up; > + drive-strength-microamp = <32>; > + }; > + }; > +}; No common file is needed at least for now. You can put it in the board dts. Also, squash this into the next patch as it is more related to the uart. > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi > index 0777bf9e01183..a2d5f7d4a942a 100644 > --- a/arch/riscv/boot/dts/spacemit/k1.dtsi > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi > @@ -416,6 +416,11 @@ uart9: serial@d4017800 { > status = "disabled"; > }; > > + pinctrl: pinctrl@d401e000 { > + compatible = "spacemit,k1-pinctrl"; > + reg = <0x0 0xd401e000 0x0 0x400>; > + }; > + > plic: interrupt-controller@e0000000 { > compatible = "spacemit,k1-plic", "sifive,plic-1.0.0"; > reg = <0x0 0xe0000000 0x0 0x4000000>; > > -- > 2.45.2 >
Hi Inochi: On 15:55 Mon 26 Aug , Inochi Amaoto wrote: > On Sun, Aug 25, 2024 at 01:10:04PM GMT, Yixun Lan wrote: > > Add pinctrl device tree data to SpacemiT's K1 SoC. > > > > Signed-off-by: Yixun Lan <dlan@gentoo.org> > > --- > > Note, only minimal device tree data added in this series, > > which just try to demonstrate this pinctrl driver, but > > more dt data can be added later, in separate patches. > > --- > > arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 19 +++++++++++++++++++ > > arch/riscv/boot/dts/spacemit/k1.dtsi | 5 +++++ > > 2 files changed, 24 insertions(+) > > > > diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi > > new file mode 100644 > > index 0000000000000..38ccaad1209f5 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi > > @@ -0,0 +1,19 @@ > > +// SPDX-License-Identifier: GPL-2.0 OR MIT > > +/* > > + * Copyright (c) 2024 Yixun Lan <dlan@gentoo.org> > > + */ > > + > > +#include <dt-bindings/gpio/gpio.h> > > +#include <dt-bindings/pinctrl/spacemit,k1-pinctrl.h> > > + > > > > +&pinctrl { > > + uart0_2_cfg: uart0-2-cfg { > > + uart0-2-pins { > > + pinmux = <K1_PADCONF(GPIO_68, 2)>, > > + <K1_PADCONF(GPIO_69, 2)>; > > + > > + bias-pull-up; > > + drive-strength-microamp = <32>; > > + }; > > + }; > > +}; > > No common file is needed at least for now. You can put it > in the board dts. Also, squash this into the next patch as > it is more related to the uart. > given that there are many K1 SoC boards on the market, having a separated pinctrl dts file makes more sense, this will maximize data sharing. the problem here that I haven't populated too many pinctrl cfgs in this file, so it looks quite slim.. but the plan was to put all pinctrl meta data here even if not used by particular board. so, I would like to keep current struture unless I'm wrong here.
diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi new file mode 100644 index 0000000000000..38ccaad1209f5 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2024 Yixun Lan <dlan@gentoo.org> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/spacemit,k1-pinctrl.h> + +&pinctrl { + uart0_2_cfg: uart0-2-cfg { + uart0-2-pins { + pinmux = <K1_PADCONF(GPIO_68, 2)>, + <K1_PADCONF(GPIO_69, 2)>; + + bias-pull-up; + drive-strength-microamp = <32>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 0777bf9e01183..a2d5f7d4a942a 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -416,6 +416,11 @@ uart9: serial@d4017800 { status = "disabled"; }; + pinctrl: pinctrl@d401e000 { + compatible = "spacemit,k1-pinctrl"; + reg = <0x0 0xd401e000 0x0 0x400>; + }; + plic: interrupt-controller@e0000000 { compatible = "spacemit,k1-plic", "sifive,plic-1.0.0"; reg = <0x0 0xe0000000 0x0 0x4000000>;
Add pinctrl device tree data to SpacemiT's K1 SoC. Signed-off-by: Yixun Lan <dlan@gentoo.org> --- Note, only minimal device tree data added in this series, which just try to demonstrate this pinctrl driver, but more dt data can be added later, in separate patches. --- arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 19 +++++++++++++++++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 5 +++++ 2 files changed, 24 insertions(+)