diff mbox series

[v6,4/4] PCI: qcom: Add RX margining settings for 16.0 GT/s

Message ID 20240904-pci-qcom-gen4-stability-v6-4-ec39f7ae3f62@linaro.org (mailing list archive)
State Superseded
Headers show
Series PCI: qcom: Add 16.0 GT/s equalization and margining settings | expand

Commit Message

Manivannan Sadhasivam via B4 Relay Sept. 4, 2024, 7:12 a.m. UTC
From: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>

Add RX lane margining settings for 16.0 GT/s (GEN 4) data rate. These
settings improve link stability while operating at high date rates and
helps to improve signal quality.

Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[mani: dropped the code refactoring and minor changes]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/pci/controller/dwc/pcie-designware.h  | 18 ++++++++++++++++
 drivers/pci/controller/dwc/pcie-qcom-common.c | 31 +++++++++++++++++++++++++++
 drivers/pci/controller/dwc/pcie-qcom-common.h |  1 +
 drivers/pci/controller/dwc/pcie-qcom-ep.c     |  4 +++-
 drivers/pci/controller/dwc/pcie-qcom.c        |  4 +++-
 5 files changed, 56 insertions(+), 2 deletions(-)

Comments

Johan Hovold Sept. 4, 2024, 9:53 a.m. UTC | #1
On Wed, Sep 04, 2024 at 12:42:00PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> From: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
> 
> Add RX lane margining settings for 16.0 GT/s (GEN 4) data rate. These
> settings improve link stability while operating at high date rates and
> helps to improve signal quality.
> 
> Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> [mani: dropped the code refactoring and minor changes]
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>  drivers/pci/controller/dwc/pcie-designware.h  | 18 ++++++++++++++++
>  drivers/pci/controller/dwc/pcie-qcom-common.c | 31 +++++++++++++++++++++++++++
>  drivers/pci/controller/dwc/pcie-qcom-common.h |  1 +
>  drivers/pci/controller/dwc/pcie-qcom-ep.c     |  4 +++-
>  drivers/pci/controller/dwc/pcie-qcom.c        |  4 +++-
>  5 files changed, 56 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 51744ad25575..f5be99731f7e 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -209,6 +209,24 @@
>  
>  #define PCIE_PL_CHK_REG_ERR_ADDR			0xB28
>  
> +/*
> + * 16.0 GT/s (GEN4) lane margining register definitions

nit: Gen 4?

> + */
> +#define GEN4_LANE_MARGINING_1_OFF		0xb80

nit: upper case hex

> +#define MARGINING_MAX_VOLTAGE_OFFSET		GENMASK(29, 24)
> +#define MARGINING_NUM_VOLTAGE_STEPS		GENMASK(22, 16)
> +#define MARGINING_MAX_TIMING_OFFSET		GENMASK(13, 8)
> +#define MARGINING_NUM_TIMING_STEPS		GENMASK(5, 0)
> +
> +#define GEN4_LANE_MARGINING_2_OFF		0xb84

Same here

> +#define MARGINING_IND_ERROR_SAMPLER		BIT(28)
> +#define MARGINING_SAMPLE_REPORTING_METHOD	BIT(27)
> +#define MARGINING_IND_LEFT_RIGHT_TIMING		BIT(26)
> +#define MARGINING_IND_UP_DOWN_VOLTAGE		BIT(25)
> +#define MARGINING_VOLTAGE_SUPPORTED		BIT(24)
> +#define MARGINING_MAXLANES			GENMASK(20, 16)
> +#define MARGINING_SAMPLE_RATE_TIMING		GENMASK(13, 8)
> +#define MARGINING_SAMPLE_RATE_VOLTAGE		GENMASK(5, 0)
>  /*
>   * iATU Unroll-specific register definitions
>   * From 4.80 core version the address translation will be made by unroll
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c
> index dc7d93db9dc5..99b75e7f085d 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-common.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c
> @@ -43,3 +43,34 @@ void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci)
>  	dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg);
>  }
>  EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_eq_settings);
> +
> +void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci)

I'd try to find a shorter symbol name here, "settings" seems redundant
after "set". Perhaps just

	qcom_pcie_common_enable_lane_margining()

or

	qcom_pcie_common_enable_16gt_lane_margining()?

if these settings are indeed specific to 16 GT/s. But perhaps it's
better to let the helper honour pci->max_link_speed if different
settings will later be needed for higher speeds:

	if (pcie_link_speed[pci->max_link_speed] >= PCIE_SPEED_16_0GT)
		qcom_pcie_common_enable_lane_margining(pci)

>  void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci);
> +void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci);

And maybe something similar for the eq settings for symmetry.

Johan
Manivannan Sadhasivam Sept. 4, 2024, 4:04 p.m. UTC | #2
On Wed, Sep 04, 2024 at 11:53:42AM +0200, Johan Hovold wrote:
> On Wed, Sep 04, 2024 at 12:42:00PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> > From: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
> > 
> > Add RX lane margining settings for 16.0 GT/s (GEN 4) data rate. These
> > settings improve link stability while operating at high date rates and
> > helps to improve signal quality.
> > 
> > Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > [mani: dropped the code refactoring and minor changes]
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> >  drivers/pci/controller/dwc/pcie-designware.h  | 18 ++++++++++++++++
> >  drivers/pci/controller/dwc/pcie-qcom-common.c | 31 +++++++++++++++++++++++++++
> >  drivers/pci/controller/dwc/pcie-qcom-common.h |  1 +
> >  drivers/pci/controller/dwc/pcie-qcom-ep.c     |  4 +++-
> >  drivers/pci/controller/dwc/pcie-qcom.c        |  4 +++-
> >  5 files changed, 56 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index 51744ad25575..f5be99731f7e 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -209,6 +209,24 @@
> >  
> >  #define PCIE_PL_CHK_REG_ERR_ADDR			0xB28
> >  
> > +/*
> > + * 16.0 GT/s (GEN4) lane margining register definitions
> 
> nit: Gen 4?
> 
> > + */
> > +#define GEN4_LANE_MARGINING_1_OFF		0xb80
> 
> nit: upper case hex
> 
> > +#define MARGINING_MAX_VOLTAGE_OFFSET		GENMASK(29, 24)
> > +#define MARGINING_NUM_VOLTAGE_STEPS		GENMASK(22, 16)
> > +#define MARGINING_MAX_TIMING_OFFSET		GENMASK(13, 8)
> > +#define MARGINING_NUM_TIMING_STEPS		GENMASK(5, 0)
> > +
> > +#define GEN4_LANE_MARGINING_2_OFF		0xb84
> 
> Same here
> 
> > +#define MARGINING_IND_ERROR_SAMPLER		BIT(28)
> > +#define MARGINING_SAMPLE_REPORTING_METHOD	BIT(27)
> > +#define MARGINING_IND_LEFT_RIGHT_TIMING		BIT(26)
> > +#define MARGINING_IND_UP_DOWN_VOLTAGE		BIT(25)
> > +#define MARGINING_VOLTAGE_SUPPORTED		BIT(24)
> > +#define MARGINING_MAXLANES			GENMASK(20, 16)
> > +#define MARGINING_SAMPLE_RATE_TIMING		GENMASK(13, 8)
> > +#define MARGINING_SAMPLE_RATE_VOLTAGE		GENMASK(5, 0)
> >  /*
> >   * iATU Unroll-specific register definitions
> >   * From 4.80 core version the address translation will be made by unroll
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c
> > index dc7d93db9dc5..99b75e7f085d 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom-common.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c
> > @@ -43,3 +43,34 @@ void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci)
> >  	dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg);
> >  }
> >  EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_eq_settings);
> > +
> > +void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci)
> 
> I'd try to find a shorter symbol name here, "settings" seems redundant
> after "set". Perhaps just
> 
> 	qcom_pcie_common_enable_lane_margining()
> 
> or
> 
> 	qcom_pcie_common_enable_16gt_lane_margining()?
> 

This one looks better. Since lane margining is implemented in the receiver, we
don't really need 'rx' in the function name.

> if these settings are indeed specific to 16 GT/s. But perhaps it's
> better to let the helper honour pci->max_link_speed if different
> settings will later be needed for higher speeds:
> 
> 	if (pcie_link_speed[pci->max_link_speed] >= PCIE_SPEED_16_0GT)
> 		qcom_pcie_common_enable_lane_margining(pci)
> 

I did thought about it during the review, but this setting claims to be for 16
GT/s only. So I wouldn't recommend applying it to other speeds without checking 
with Qcom.

Unfortunately, I'm on vacation for 2 weeks and have limited access to Qcom
internal docs/chat. So won't be able to check it soon. If Shashank could check
it, it is fine. But on the conservative side, let's stick to 16 GT/s only?

- Mani

> >  void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci);
> > +void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci);
> 
> And maybe something similar for the eq settings for symmetry.
> 
> Johan
Shashank Babu Chinta Venkata Sept. 4, 2024, 8:48 p.m. UTC | #3
On 9/4/24 09:04, Manivannan Sadhasivam wrote:
> On Wed, Sep 04, 2024 at 11:53:42AM +0200, Johan Hovold wrote:
>> On Wed, Sep 04, 2024 at 12:42:00PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
>>> From: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
>>>
>>> Add RX lane margining settings for 16.0 GT/s (GEN 4) data rate. These
>>> settings improve link stability while operating at high date rates and
>>> helps to improve signal quality.
>>>
>>> Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
>>> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>>> [mani: dropped the code refactoring and minor changes]
>>> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>>> ---
>>>  drivers/pci/controller/dwc/pcie-designware.h  | 18 ++++++++++++++++
>>>  drivers/pci/controller/dwc/pcie-qcom-common.c | 31 +++++++++++++++++++++++++++
>>>  drivers/pci/controller/dwc/pcie-qcom-common.h |  1 +
>>>  drivers/pci/controller/dwc/pcie-qcom-ep.c     |  4 +++-
>>>  drivers/pci/controller/dwc/pcie-qcom.c        |  4 +++-
>>>  5 files changed, 56 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
>>> index 51744ad25575..f5be99731f7e 100644
>>> --- a/drivers/pci/controller/dwc/pcie-designware.h
>>> +++ b/drivers/pci/controller/dwc/pcie-designware.h
>>> @@ -209,6 +209,24 @@
>>>  
>>>  #define PCIE_PL_CHK_REG_ERR_ADDR			0xB28
>>>  
>>> +/*
>>> + * 16.0 GT/s (GEN4) lane margining register definitions
>>
>> nit: Gen 4?
>>
>>> + */
>>> +#define GEN4_LANE_MARGINING_1_OFF		0xb80
>>
>> nit: upper case hex
>>
>>> +#define MARGINING_MAX_VOLTAGE_OFFSET		GENMASK(29, 24)
>>> +#define MARGINING_NUM_VOLTAGE_STEPS		GENMASK(22, 16)
>>> +#define MARGINING_MAX_TIMING_OFFSET		GENMASK(13, 8)
>>> +#define MARGINING_NUM_TIMING_STEPS		GENMASK(5, 0)
>>> +
>>> +#define GEN4_LANE_MARGINING_2_OFF		0xb84
>>
>> Same here
>>
>>> +#define MARGINING_IND_ERROR_SAMPLER		BIT(28)
>>> +#define MARGINING_SAMPLE_REPORTING_METHOD	BIT(27)
>>> +#define MARGINING_IND_LEFT_RIGHT_TIMING		BIT(26)
>>> +#define MARGINING_IND_UP_DOWN_VOLTAGE		BIT(25)
>>> +#define MARGINING_VOLTAGE_SUPPORTED		BIT(24)
>>> +#define MARGINING_MAXLANES			GENMASK(20, 16)
>>> +#define MARGINING_SAMPLE_RATE_TIMING		GENMASK(13, 8)
>>> +#define MARGINING_SAMPLE_RATE_VOLTAGE		GENMASK(5, 0)
>>>  /*
>>>   * iATU Unroll-specific register definitions
>>>   * From 4.80 core version the address translation will be made by unroll
>>> diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c
>>> index dc7d93db9dc5..99b75e7f085d 100644
>>> --- a/drivers/pci/controller/dwc/pcie-qcom-common.c
>>> +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c
>>> @@ -43,3 +43,34 @@ void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci)
>>>  	dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg);
>>>  }
>>>  EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_eq_settings);
>>> +
>>> +void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci)
>>
>> I'd try to find a shorter symbol name here, "settings" seems redundant
>> after "set". Perhaps just
>>
>> 	qcom_pcie_common_enable_lane_margining()
>>
>> or
>>
>> 	qcom_pcie_common_enable_16gt_lane_margining()?
>>
> 
> This one looks better. Since lane margining is implemented in the receiver, we
> don't really need 'rx' in the function name.
> 
>> if these settings are indeed specific to 16 GT/s. But perhaps it's
>> better to let the helper honour pci->max_link_speed if different
>> settings will later be needed for higher speeds:
>>
>> 	if (pcie_link_speed[pci->max_link_speed] >= PCIE_SPEED_16_0GT)
>> 		qcom_pcie_common_enable_lane_margining(pci)
>>
> 
> I did thought about it during the review, but this setting claims to be for 16
> GT/s only. So I wouldn't recommend applying it to other speeds without checking 
> with Qcom.
> 
> Unfortunately, I'm on vacation for 2 weeks and have limited access to Qcom
> internal docs/chat. So won't be able to check it soon. If Shashank could check
> it, it is fine. But on the conservative side, let's stick to 16 GT/s only?
> 
> - Mani

Yes Mani I think we have to stick to 16 GT/s only for now as we haven't characterized 32 GT/s yet.


> 
>>>  void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci);
>>> +void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci);
>>
>> And maybe something similar for the eq settings for symmetry.
>>
>> Johan
>
Johan Hovold Sept. 5, 2024, 7 a.m. UTC | #4
On Wed, Sep 04, 2024 at 01:48:09PM -0700, Shashank Babu Chinta Venkata wrote:
> On 9/4/24 09:04, Manivannan Sadhasivam wrote:
> > On Wed, Sep 04, 2024 at 11:53:42AM +0200, Johan Hovold wrote:
> >> On Wed, Sep 04, 2024 at 12:42:00PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> >>> From: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>

> >>> +void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci)
> >>
> >> I'd try to find a shorter symbol name here, "settings" seems redundant
> >> after "set". Perhaps just
> >>
> >> 	qcom_pcie_common_enable_lane_margining()
> >>
> >> or
> >>
> >> 	qcom_pcie_common_enable_16gt_lane_margining()?
> >>
> > 
> > This one looks better. Since lane margining is implemented in the receiver, we
> > don't really need 'rx' in the function name.
> > 
> >> if these settings are indeed specific to 16 GT/s. But perhaps it's
> >> better to let the helper honour pci->max_link_speed if different
> >> settings will later be needed for higher speeds:
> >>
> >> 	if (pcie_link_speed[pci->max_link_speed] >= PCIE_SPEED_16_0GT)
> >> 		qcom_pcie_common_enable_lane_margining(pci)
> >>
> > 
> > I did thought about it during the review, but this setting claims to be for 16
> > GT/s only. So I wouldn't recommend applying it to other speeds without checking 
> > with Qcom.

Yeah, this was more an example of what the code may look like eventually
since IIUC anything above Gen4 will need lane margining.

> > Unfortunately, I'm on vacation for 2 weeks and have limited access to Qcom
> > internal docs/chat. So won't be able to check it soon. If Shashank could check
> > it, it is fine. But on the conservative side, let's stick to 16 GT/s only?

> Yes Mani I think we have to stick to 16 GT/s only for now as we
> haven't characterized 32 GT/s yet.

Sounds good. We can always generalise or rename these functions later
(e.g. when adding support for higher speeds).

> >>>  void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci);
> >>> +void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci);

Perhaps just dropping "_settings" (and replacing "_rx") is enough for
now? So something like:

	qcom_pcie_common_set_16gt_equalization()
	qcom_pcie_common_set_16gt_lane_margining()

A bit shorter and pretty self-explaining.

Johan
diff mbox series

Patch

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 51744ad25575..f5be99731f7e 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -209,6 +209,24 @@ 
 
 #define PCIE_PL_CHK_REG_ERR_ADDR			0xB28
 
+/*
+ * 16.0 GT/s (GEN4) lane margining register definitions
+ */
+#define GEN4_LANE_MARGINING_1_OFF		0xb80
+#define MARGINING_MAX_VOLTAGE_OFFSET		GENMASK(29, 24)
+#define MARGINING_NUM_VOLTAGE_STEPS		GENMASK(22, 16)
+#define MARGINING_MAX_TIMING_OFFSET		GENMASK(13, 8)
+#define MARGINING_NUM_TIMING_STEPS		GENMASK(5, 0)
+
+#define GEN4_LANE_MARGINING_2_OFF		0xb84
+#define MARGINING_IND_ERROR_SAMPLER		BIT(28)
+#define MARGINING_SAMPLE_REPORTING_METHOD	BIT(27)
+#define MARGINING_IND_LEFT_RIGHT_TIMING		BIT(26)
+#define MARGINING_IND_UP_DOWN_VOLTAGE		BIT(25)
+#define MARGINING_VOLTAGE_SUPPORTED		BIT(24)
+#define MARGINING_MAXLANES			GENMASK(20, 16)
+#define MARGINING_SAMPLE_RATE_TIMING		GENMASK(13, 8)
+#define MARGINING_SAMPLE_RATE_VOLTAGE		GENMASK(5, 0)
 /*
  * iATU Unroll-specific register definitions
  * From 4.80 core version the address translation will be made by unroll
diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c
index dc7d93db9dc5..99b75e7f085d 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-common.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-common.c
@@ -43,3 +43,34 @@  void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci)
 	dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg);
 }
 EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_eq_settings);
+
+void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci)
+{
+	u32 reg;
+
+	reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF);
+	reg &= ~(MARGINING_MAX_VOLTAGE_OFFSET |
+		MARGINING_NUM_VOLTAGE_STEPS |
+		MARGINING_MAX_TIMING_OFFSET |
+		MARGINING_NUM_TIMING_STEPS);
+	reg |= FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) |
+		FIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) |
+		FIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) |
+		FIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10);
+	dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg);
+
+	reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF);
+	reg |= MARGINING_IND_ERROR_SAMPLER |
+		MARGINING_SAMPLE_REPORTING_METHOD |
+		MARGINING_IND_LEFT_RIGHT_TIMING |
+		MARGINING_VOLTAGE_SUPPORTED;
+	reg &= ~(MARGINING_IND_UP_DOWN_VOLTAGE |
+		MARGINING_MAXLANES |
+		MARGINING_SAMPLE_RATE_TIMING |
+		MARGINING_SAMPLE_RATE_VOLTAGE);
+	reg |= FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) |
+		FIELD_PREP(MARGINING_SAMPLE_RATE_TIMING, 0x3f) |
+		FIELD_PREP(MARGINING_SAMPLE_RATE_VOLTAGE, 0x3f);
+	dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg);
+}
+EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_rx_margining_settings);
diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.h b/drivers/pci/controller/dwc/pcie-qcom-common.h
index 259e04b7bdf9..e9ddc901082e 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-common.h
+++ b/drivers/pci/controller/dwc/pcie-qcom-common.h
@@ -6,3 +6,4 @@ 
 #include "pcie-designware.h"
 
 void qcom_pcie_common_set_16gt_eq_settings(struct dw_pcie *pci);
+void qcom_pcie_common_set_16gt_rx_margining_settings(struct dw_pcie *pci);
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index af83470216e8..5c220f2ecafe 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -487,8 +487,10 @@  static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
 		goto err_disable_resources;
 	}
 
-	if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT)
+	if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) {
 		qcom_pcie_common_set_16gt_eq_settings(pci);
+		qcom_pcie_common_set_16gt_rx_margining_settings(pci);
+	}
 
 	/*
 	 * The physical address of the MMIO region which is exposed as the BAR
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 2742e82fdcb3..b0b1d8d34279 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -284,8 +284,10 @@  static int qcom_pcie_start_link(struct dw_pcie *pci)
 {
 	struct qcom_pcie *pcie = to_qcom_pcie(pci);
 
-	if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT)
+	if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) {
 		qcom_pcie_common_set_16gt_eq_settings(pci);
+		qcom_pcie_common_set_16gt_rx_margining_settings(pci);
+	}
 
 	/* Enable Link Training state machine */
 	if (pcie->cfg->ops->ltssm_enable)