| Message ID | 20241217100359.4017214-2-quic_varada@quicinc.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | Add PCIe support for Qualcomm IPQ5332 | expand |
On Tue, Dec 17, 2024 at 03:33:55PM +0530, Varadarajan Narayanan wrote: > From: Nitheesh Sekar <quic_nsekar@quicinc.com> > > Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332. > > Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > v3: Fix compatible string to be similar to other phys and rename file accordingly > Fix clocks minItems -> maxItems I think there was just one clock, so you increased it to two. > Change one of the maintainer from Sricharan to Varadarajan > > v2: Rename the file to match the compatible > Drop 'driver' from title > Dropped 'clock-names' > Fixed 'reset-names' > -- > .../phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 82 +++++++++++++++++++ > 1 file changed, 82 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml > new file mode 100644 > index 000000000000..0634d4fb85d1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml > @@ -0,0 +1,82 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm UNIPHY PCIe 28LP PHY > + > +maintainers: > + - Nitheesh Sekar <quic_nsekar@quicinc.com> > + - Varadarajan Narayanan <quic_varada@quicinc.com> > + > +description: > + PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC > + > +properties: > + compatible: > + enum: > + - qcom,ipq5332-uniphy-gen3x1-pcie-phy > + - qcom,ipq5332-uniphy-gen3x2-pcie-phy > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 2 I should have been more specific last time, but I assumed you will take other bindings as example. well, so now proper review: you need to list tiems. > + > + resets: > + minItems: 2 > + maxItems: 3 No answer to my previous question. Question stands. > + > + reset-names: > + minItems: 2 > + items: > + - const: phy > + - const: phy_ahb > + - const: phy_cfg > + > + "#phy-cells": > + const: 0 > + > + "#clock-cells": > + const: 0 > + > + clock-output-names: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - resets > + - reset-names > + - clocks Keep the same order as in properties block. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml new file mode 100644 index 000000000000..0634d4fb85d1 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm UNIPHY PCIe 28LP PHY + +maintainers: + - Nitheesh Sekar <quic_nsekar@quicinc.com> + - Varadarajan Narayanan <quic_varada@quicinc.com> + +description: + PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC + +properties: + compatible: + enum: + - qcom,ipq5332-uniphy-gen3x1-pcie-phy + - qcom,ipq5332-uniphy-gen3x2-pcie-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + resets: + minItems: 2 + maxItems: 3 + + reset-names: + minItems: 2 + items: + - const: phy + - const: phy_ahb + - const: phy_cfg + + "#phy-cells": + const: 0 + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - reg + - resets + - reset-names + - clocks + - "#phy-cells" + - "#clock-cells" + - clock-output-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,ipq5332-gcc.h> + + pcie0_phy: phy@4b0000 { + compatible = "qcom,ipq5332-uniphy-gen3x1-pcie-phy"; + reg = <0x004b0000 0x800>; + + clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; + + resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>; + reset-names = "phy", + "phy_ahb", + "phy_cfg"; + + #clock-cells = <0>; + clock-output-names = "pcie0_pipe_clk_src"; + + #phy-cells = <0>; + };