diff mbox series

[v2,4/7] dt-bindings: riscv: add Sxctr ISA extension description

Message ID 20250116230955.867152-5-rkanwal@rivosinc.com (mailing list archive)
State New
Headers show
Series riscv: pmu: Add support for Control Transfer Records Ext. | expand

Checks

Context Check Description
conchuod/vmtest-fixes-PR fail merge-conflict

Commit Message

Rajnesh Kanwal Jan. 16, 2025, 11:09 p.m. UTC
Add the S[m|s]ctr ISA extension description.

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
---
 .../devicetree/bindings/riscv/extensions.yaml      | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

Comments

Krzysztof Kozlowski Jan. 17, 2025, 7:26 a.m. UTC | #1
On 17/01/2025 00:09, Rajnesh Kanwal wrote:
> Add the S[m|s]ctr ISA extension description.
> 
> Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
> ---
>  .../devicetree/bindings/riscv/extensions.yaml      | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)

<form letter>
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.

Tools like b4 or scripts/get_maintainer.pl provide you proper list of
people, so fix your workflow. Tools might also fail if you work on some
ancient tree (don't, instead use mainline) or work on fork of kernel
(don't, instead use mainline). Just use b4 and everything should be
fine, although remember about `b4 prep --auto-to-cc` if you added new
patches to the patchset.

You missed at least devicetree list (maybe more), so this won't be
tested by automated tooling. Performing review on untested code might be
a waste of time.

Please kindly resend and include all necessary To/Cc entries.
</form letter>

Best regards,
Krzysztof
Rajnesh Kanwal Jan. 20, 2025, 2:31 p.m. UTC | #2
Hi Krzysztof,

Sorry my bad. I will keep this in mind next time.
Thanks for pointing it out.

- Rajnesh

On Fri, Jan 17, 2025 at 7:26 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 17/01/2025 00:09, Rajnesh Kanwal wrote:
> > Add the S[m|s]ctr ISA extension description.
> >
> > Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
> > ---
> >  .../devicetree/bindings/riscv/extensions.yaml      | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
>
> <form letter>
> Please use scripts/get_maintainers.pl to get a list of necessary people
> and lists to CC. It might happen, that command when run on an older
> kernel, gives you outdated entries. Therefore please be sure you base
> your patches on recent Linux kernel.
>
> Tools like b4 or scripts/get_maintainer.pl provide you proper list of
> people, so fix your workflow. Tools might also fail if you work on some
> ancient tree (don't, instead use mainline) or work on fork of kernel
> (don't, instead use mainline). Just use b4 and everything should be
> fine, although remember about `b4 prep --auto-to-cc` if you added new
> patches to the patchset.
>
> You missed at least devicetree list (maybe more), so this won't be
> tested by automated tooling. Performing review on untested code might be
> a waste of time.
>
> Please kindly resend and include all necessary To/Cc entries.
> </form letter>
>
> Best regards,
> Krzysztof
Conor Dooley Jan. 20, 2025, 6:49 p.m. UTC | #3
On Thu, Jan 16, 2025 at 11:09:52PM +0000, Rajnesh Kanwal wrote:
> Add the S[m|s]ctr ISA extension description.
> 
> Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
> ---
>  .../devicetree/bindings/riscv/extensions.yaml      | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 848354e3048f..8322503f0773 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -167,6 +167,13 @@ properties:
>  	    extension allows other ISA extension to use indirect CSR access
>  	    mechanism in M-mode.
>  
> +        - const: smctr
> +          description: |
> +            The standard Smctr supervisor-level extension for the machine mode
> +            to enable recording limited branch history in a register-accessible
> +            internal core storage. Smctr depend on both the implementation of
> +            S-mode and the Sscsrind extension.

Please, like the other extensions, cite the commit (and repo) where the
extension was frozen or ratified.

> +
>  	- const: sscsrind
>            description: |
>              The standard Sscsrind supervisor-level extension extends the
> @@ -193,6 +200,13 @@ properties:
>              and mode-based filtering as ratified at commit 01d1df0 ("Add ability
>              to manually trigger workflow. (#2)") of riscv-count-overflow.
>  
> +        - const: ssctr
> +          description: |
> +            The standard Ssctr supervisor-level extension enables recording of
> +            limited branch history in a register-accessible internal core
> +            storage. Ssctr depend on both the implementation of S-mode and the
> +            Sscsrind extension.
> +
>          - const: ssnpm
>            description: |
>              The standard Ssnpm extension for next-mode pointer masking as
> -- 
> 2.34.1
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 848354e3048f..8322503f0773 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -167,6 +167,13 @@  properties:
 	    extension allows other ISA extension to use indirect CSR access
 	    mechanism in M-mode.
 
+        - const: smctr
+          description: |
+            The standard Smctr supervisor-level extension for the machine mode
+            to enable recording limited branch history in a register-accessible
+            internal core storage. Smctr depend on both the implementation of
+            S-mode and the Sscsrind extension.
+
 	- const: sscsrind
           description: |
             The standard Sscsrind supervisor-level extension extends the
@@ -193,6 +200,13 @@  properties:
             and mode-based filtering as ratified at commit 01d1df0 ("Add ability
             to manually trigger workflow. (#2)") of riscv-count-overflow.
 
+        - const: ssctr
+          description: |
+            The standard Ssctr supervisor-level extension enables recording of
+            limited branch history in a register-accessible internal core
+            storage. Ssctr depend on both the implementation of S-mode and the
+            Sscsrind extension.
+
         - const: ssnpm
           description: |
             The standard Ssnpm extension for next-mode pointer masking as