| Message ID | 20250127173550.1222427-2-matthew.gerlach@linux.intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add PCIe Root Port support for Agilex family of chips | expand |
On 27/01/2025 18:35, Matthew Gerlach wrote: > Add the compatible bindings for the three variants of Agilex > PCIe Hard IP. > > Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> > Reviewed-by: Rob Herring (Arm) <robh@kernel.org> > --- > v3: > - Remove accepted patches from patch set. > --- > .../devicetree/bindings/pci/altr,pcie-root-port.yaml | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml > index 52533fccc134..ca9691ec87d2 100644 > --- a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml > +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml > @@ -12,9 +12,18 @@ maintainers: > > properties: > compatible: > + description: altr,pcie-root-port-1.0 is used for the Cyclone5 > + family of chips. The Stratix10 family of chips is supported > + by altr,pcie-root-port-2.0. The Agilex family of chips has > + three variants of PCIe Hard IP referred to as the f-tile, p-tile, > + and r-tile. Has three in the same time? Or one of three? Your board DTS said you have exactly one, so this comment is confusing. Best regards, Krzysztof
On Thu, 30 Jan 2025, Krzysztof Kozlowski wrote: > On 27/01/2025 18:35, Matthew Gerlach wrote: >> Add the compatible bindings for the three variants of Agilex >> PCIe Hard IP. >> >> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> >> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> >> --- >> v3: >> - Remove accepted patches from patch set. >> --- >> .../devicetree/bindings/pci/altr,pcie-root-port.yaml | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml >> index 52533fccc134..ca9691ec87d2 100644 >> --- a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml >> +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml >> @@ -12,9 +12,18 @@ maintainers: >> >> properties: >> compatible: >> + description: altr,pcie-root-port-1.0 is used for the Cyclone5 >> + family of chips. The Stratix10 family of chips is supported >> + by altr,pcie-root-port-2.0. The Agilex family of chips has >> + three variants of PCIe Hard IP referred to as the f-tile, p-tile, >> + and r-tile. > > > Has three in the same time? Or one of three? Your board DTS said you > have exactly one, so this comment is confusing. I will clarify this comment to reflect that a particular instantiantion will only have one of the tiles. > > > Best regards, > Krzysztof > Thanks for the feedback, Matthew Gerlach
diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml index 52533fccc134..ca9691ec87d2 100644 --- a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml @@ -12,9 +12,18 @@ maintainers: properties: compatible: + description: altr,pcie-root-port-1.0 is used for the Cyclone5 + family of chips. The Stratix10 family of chips is supported + by altr,pcie-root-port-2.0. The Agilex family of chips has + three variants of PCIe Hard IP referred to as the f-tile, p-tile, + and r-tile. + enum: - altr,pcie-root-port-1.0 - altr,pcie-root-port-2.0 + - altr,pcie-root-port-3.0-f-tile + - altr,pcie-root-port-3.0-p-tile + - altr,pcie-root-port-3.0-r-tile reg: items: