Message ID | 20250128062708.573662-4-quic_varada@quicinc.com (mailing list archive) |
---|---|
State | New |
Delegated to: | Krzysztof WilczyĆski |
Headers | show |
Series | Add PCIe support for Qualcomm IPQ5332 | expand |
On Tue, Jan 28, 2025 at 11:57:04AM +0530, Varadarajan Narayanan wrote: > All DT entries except "reg" is similar between ipq5332 and > ipq9574. ipq9574 has 5 registers while ipq5332 has 6. MHI is the > additional (i.e. sixth entry). Since this matches with the > sdx55's "reg" definition which allows for 5 or 6 registers, > combine ipq9574 with sdx55. > > This change is to prepare ipq9574 to be used as ipq5332's > fallback compatible. Nit: since there are apparently other fixes coming for this series, rewrap all the commit logs to fill 75 columns (so they fit in 80 columns even after "git log" indents them). No point in artificially short lines.
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 7235d6554cfb..4b4927178abc 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -169,7 +169,6 @@ allOf: enum: - qcom,pcie-ipq6018 - qcom,pcie-ipq8074-gen3 - - qcom,pcie-ipq9574 then: properties: reg: @@ -210,6 +209,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq9574 - qcom,pcie-sdx55 then: properties: