| Message ID | 20250203013730.269558-4-e@freeshell.de (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: dts: starfive: jh7110-common: Sync downstream U-Boot changes | expand |
| Context | Check | Description |
|---|---|---|
| bjorn/pre-ci_am | success | Success |
| bjorn/build-rv32-defconfig | success | build-rv32-defconfig |
| bjorn/build-rv64-clang-allmodconfig | success | build-rv64-clang-allmodconfig |
| bjorn/build-rv64-gcc-allmodconfig | success | build-rv64-gcc-allmodconfig |
| bjorn/build-rv64-nommu-k210-defconfig | success | build-rv64-nommu-k210-defconfig |
| bjorn/build-rv64-nommu-k210-virt | success | build-rv64-nommu-k210-virt |
| bjorn/checkpatch | success | checkpatch |
| bjorn/dtb-warn-rv64 | success | dtb-warn-rv64 |
| bjorn/header-inline | success | header-inline |
| bjorn/kdoc | success | kdoc |
| bjorn/module-param | success | module-param |
| bjorn/verify-fixes | success | verify-fixes |
| bjorn/verify-signedoff | success | verify-signedoff |
On 2/3/2025 9:37 AM, E Shattow wrote: > Set uart0 clock-frequency for better compatibility with operating system > and downstream boot loader SPL secondary program loader. > > Signed-off-by: E Shattow <e@freeshell.de> > --- > arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > index 8a59c3001339..6bb13af82147 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > @@ -635,6 +635,7 @@ GPOEN_DISABLE, > }; > > &uart0 { > + clock-frequency = <24000000>; > pinctrl-names = "default"; > pinctrl-0 = <&uart0_pins>; > status = "okay"; Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Best regards, Hal
E Shattow wrote: > Set uart0 clock-frequency for better compatibility with operating system > and downstream boot loader SPL secondary program loader. > > Signed-off-by: E Shattow <e@freeshell.de> > --- > arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > index 8a59c3001339..6bb13af82147 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > @@ -635,6 +635,7 @@ GPOEN_DISABLE, > }; > > &uart0 { > + clock-frequency = <24000000>; > pinctrl-names = "default"; > pinctrl-0 = <&uart0_pins>; > status = "okay"; The uart0 node already has a reference to the uart0_core clock, so it shouldn't need this property. /Emil
diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index 8a59c3001339..6bb13af82147 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -635,6 +635,7 @@ GPOEN_DISABLE, }; &uart0 { + clock-frequency = <24000000>; pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay";
Set uart0 clock-frequency for better compatibility with operating system and downstream boot loader SPL secondary program loader. Signed-off-by: E Shattow <e@freeshell.de> --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 1 + 1 file changed, 1 insertion(+)