diff mbox series

[v9,6/7] arm64: dts: qcom: ipq5332: Add PCIe related nodes

Message ID 20250128062708.573662-7-quic_varada@quicinc.com (mailing list archive)
State New
Delegated to: Krzysztof Wilczyński
Headers show
Series Add PCIe support for Qualcomm IPQ5332 | expand

Commit Message

Varadarajan Narayanan Jan. 28, 2025, 6:27 a.m. UTC 
From: Praveenkumar I <quic_ipkumar@quicinc.com>

Add phy and controller nodes for pcie0_x1 and pcie1_x2.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
v7: * Fix IO 'ranges' entry
    * Add root port definitions
    * Not adding 'dma-coherent' as the controller doesn't have that support
    * Remove 'bus-range' as it has default values
    * Group root complex related entries and root port related entries
      separately

v6: * Add 'num-lanes' to "pcie0_phy: phy@4b0000"
    * Earlier, some related clock rates were set in U-Boot. In
      recent versions of U-Boot this has been removed resulting
      in the phy link not coming up. To remove boot loader
      dependency add assigned-clocks and assigned-clock-rates to
      the controller nodes.
    * Not sure if 'Reviewed-by' should be dropped.

v5: Add 'num-lanes' to "pcie1_phy: phy@4b1000"
    Make ipq5332 as main and ipq9574 as fallback compatible
    Move controller nodes per address
    Having Konrad's Reviewed-By

v4: Remove 'reset-names' as driver uses bulk APIs
    Remove 'clock-output-names' as driver uses bulk APIs
    Add missing reset for pcie1_phy
    Convert 'reg-names' to a vertical list
    Move 'msi-map' before interrupts

v3: Fix compatible string for phy nodes
    Use ipq9574 as backup compatible instead of new compatible for ipq5332
    Fix mixed case hex addresses
    Add "mhi" space
    Removed unnecessary comments and stray blank lines

v2: Fix nodes' location per address
---
 arch/arm64/boot/dts/qcom/ipq5332.dtsi | 268 +++++++++++++++++++++++++-
 1 file changed, 266 insertions(+), 2 deletions(-)

Comments

Krzysztof Kozlowski Feb. 3, 2025, 4:30 p.m. UTC | #1 
On 28/01/2025 07:27, Varadarajan Narayanan wrote:
>  
> @@ -479,6 +519,230 @@ frame@b128000 {
>  				status = "disabled";
>  			};
>  		};
> +
> +		pcie1: pcie@18000000 {
> +			compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
> +			reg = <0x00088000 0x3000>,

So as Konrad pointed out now, this was never tested. It's not we who
should run tests for you. It's you.

It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
Maybe you need to update your dtschema and yamllint. Don't rely on
distro packages for dtschema and be sure you are using the latest
released dtschema.

Best regards,
Krzysztof
Varadarajan Narayanan Feb. 5, 2025, 10:49 a.m. UTC | #2 
On Mon, Feb 03, 2025 at 05:30:32PM +0100, Krzysztof Kozlowski wrote:
> On 28/01/2025 07:27, Varadarajan Narayanan wrote:
> >
> > @@ -479,6 +519,230 @@ frame@b128000 {
> >  				status = "disabled";
> >  			};
> >  		};
> > +
> > +		pcie1: pcie@18000000 {
> > +			compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
> > +			reg = <0x00088000 0x3000>,
>
> So as Konrad pointed out now, this was never tested. It's not we who
> should run tests for you. It's you.

This was tested and it did not flag an error since it is having the order
specified in the bindings. qcom,pcie.yaml has 4 reg specifications. Two of
them have 'dbi' as the first register space and two of them have 'parf' as
the first register space. Looks like the constraints with 'dbi' as the
first entry will match with pcie@xxx and the ones with 'parf' won't match.

Since IPQ5332 follows the constraints specified for sdx55 which has 'parf'
as the first entry it is not able to match with pcie@xxx value.

The initial version that was posted has the first 'reg' entry matching with
pcie@xxx (please see [1]), since it used the ipq9574 reg constraints. Based
on the feedback received [2], had to add 'mhi' area also. Since adding
'mhi' to ipq9574 would result in duplication of the sdx55 reg constraints,
ipq5332 followed sdx55's constraints resulting in the reg entries getting
reordered and the first reg entry vs pcie@xxx mismatch happened.

To resolve this, shall I reorder the sdx55 reg bindings (and the affected
DTS arch/arm/boot/dts/qcom/qcom-sdx55.dtsi). Please let me know.

1 - https://lore.kernel.org/linux-arm-msm/20241204113329.3195627-6-quic_varada@quicinc.com/
2 - https://lore.kernel.org/linux-arm-msm/6fe09de4-c94c-495d-92a4-aa902d2519ef@oss.qualcomm.com/

> It does not look like you tested the DTS against bindings. Please run
> `make dtbs_check W=1` (see
> Documentation/devicetree/bindings/writing-schema.rst or
> https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
> for instructions).
> Maybe you need to update your dtschema and yamllint. Don't rely on
> distro packages for dtschema and be sure you are using the latest
> released dtschema.

I run the following tests before posting the patches and go through the
output to see if the nodes I added/changed have any errors or if other dtbs
have been impacted by my bindings changes.

	export ARCH=arm64
	export W=1
	export DT_CHECKER_FLAGS='-v -m'
	export DT_SCHEMA_FILES=qcom
	export CHECK_DTBS=y

	pip3 install dtschema --upgrade

	make -j 16 dt_binding_check

	make -j 16 dtbs_check

	$ pip show dtschema | grep Version
	Version: 2024.11

Please let me know if I should add anything else to ensure my setup is up
to speed.

Thanks
Varada
Krzysztof Kozlowski Feb. 5, 2025, 1:47 p.m. UTC | #3 
On 05/02/2025 11:49, Varadarajan Narayanan wrote:
> On Mon, Feb 03, 2025 at 05:30:32PM +0100, Krzysztof Kozlowski wrote:
>> On 28/01/2025 07:27, Varadarajan Narayanan wrote:
>>>
>>> @@ -479,6 +519,230 @@ frame@b128000 {
>>>  				status = "disabled";
>>>  			};
>>>  		};
>>> +
>>> +		pcie1: pcie@18000000 {
>>> +			compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
>>> +			reg = <0x00088000 0x3000>,
>>
>> So as Konrad pointed out now, this was never tested. It's not we who
>> should run tests for you. It's you.
> 
> This was tested and it did not flag an error since it is having the order
> specified in the bindings. qcom,pcie.yaml has 4 reg specifications. Two of


Hm, then please paste results of dtbs_check W=1 testing. Here.

I am 100% sure you have there warning and I don't understand your
reluctance to run the tests even after pointing it out by two people.

Best regards,
Krzysztof
Varadarajan Narayanan Feb. 5, 2025, 3:35 p.m. UTC | #4 
On Wed, Feb 05, 2025 at 02:47:13PM +0100, Krzysztof Kozlowski wrote:
> On 05/02/2025 11:49, Varadarajan Narayanan wrote:
> > On Mon, Feb 03, 2025 at 05:30:32PM +0100, Krzysztof Kozlowski wrote:
> >> On 28/01/2025 07:27, Varadarajan Narayanan wrote:
> >>>
> >>> @@ -479,6 +519,230 @@ frame@b128000 {
> >>>  				status = "disabled";
> >>>  			};
> >>>  		};
> >>> +
> >>> +		pcie1: pcie@18000000 {
> >>> +			compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
> >>> +			reg = <0x00088000 0x3000>,
> >>
> >> So as Konrad pointed out now, this was never tested. It's not we who
> >> should run tests for you. It's you.
> >
> > This was tested and it did not flag an error since it is having the order
> > specified in the bindings. qcom,pcie.yaml has 4 reg specifications. Two of
>
>
> Hm, then please paste results of dtbs_check W=1 testing. Here.
>
> I am 100% sure you have there warning and I don't understand your
> reluctance to run the tests even after pointing it out by two people.

I ran the tests. Not sure which portions to paste. Have attached the full
output just in case you are interested in some other detail. Please take a
look.

Thanks
Varada

	$ grep ipq.*dtb dtbs-check.log
	  DTC [C] arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dtb
	  DTC [C] arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dtb
	  DTC [C] arch/arm64/boot/dts/qcom/ipq5332-rdp441.dtb
	  DTC [C] arch/arm64/boot/dts/qcom/ipq5332-rdp442.dtb
	  DTC [C] arch/arm64/boot/dts/qcom/ipq5332-rdp468.dtb
	  DTC [C] arch/arm64/boot/dts/qcom/ipq5332-rdp474.dtb
	  DTC [C] arch/arm64/boot/dts/qcom/ipq5424-rdp466.dtb
	  DTC [C] arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dtb: usb@8af8800: interrupts: [[0, 62, 4]] is too short
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dtb: usb@8af8800: interrupt-names: ['hs_phy_irq'] is too short
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dtb: usb@8af8800: interrupts: [[0, 62, 4]] is too short
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dtb: usb@8af8800: interrupt-names:0: 'pwr_event' was expected
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dtb: usb@8af8800: interrupt-names: ['hs_phy_irq'] is too short
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dtb: usb@8af8800: interrupts: [[0, 62, 4]] is too short
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dtb: usb@8af8800: interrupt-names: ['hs_phy_irq'] is too short
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: qusb@59000: 'vdd-supply' is a required property
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dtb: usb@8af8800: interrupts: [[0, 62, 4]] is too short
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dtb: usb@8af8800: interrupt-names:0: 'pwr_event' was expected
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dtb: usb@8af8800: interrupt-names: ['hs_phy_irq'] is too short
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: qusb@59000: 'vdda-pll-supply' is a required property
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: qusb@59000: 'vdda-phy-dpdm-supply' is a required property
	Check:  arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dtb
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: usb@70f8800: interrupt-names: ['pwr_event', 'qusb2_phy'] is too short
	Check:  arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dtb
	  DTC [C] arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb
	Check:  arch/arm64/boot/dts/qcom/ipq5424-rdp466.dtb
	Check:  arch/arm64/boot/dts/qcom/ipq5332-rdp442.dtb
	  DTC [C] arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dtb
	Check:  arch/arm64/boot/dts/qcom/ipq5332-rdp468.dtb
	Check:  arch/arm64/boot/dts/qcom/ipq5332-rdp441.dtb
	  DTC [C] arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb
	Check:  arch/arm64/boot/dts/qcom/ipq5332-rdp474.dtb
	arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: /soc@0/remoteproc@cd00000: failed to match any schema with compatible: ['qcom,ipq6018-wcss-pil']
	  DTC [C] arch/arm64/boot/dts/qcom/ipq9574-rdp418.dtb
	  DTC [C] arch/arm64/boot/dts/qcom/ipq9574-rdp433.dtb
	  DTC [C] arch/arm64/boot/dts/qcom/ipq9574-rdp449.dtb
	  DTC [C] arch/arm64/boot/dts/qcom/ipq9574-rdp453.dtb
	Check:  arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb: phy@59000: 'vdd-supply' is a required property
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb: phy@59000: 'vdda-pll-supply' is a required property
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb: phy@59000: 'vdda-phy-dpdm-supply' is a required property
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb: phy@79000: 'vdd-supply' is a required property
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb: phy@79000: 'vdda-pll-supply' is a required property
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb: phy@79000: 'vdda-phy-dpdm-supply' is a required property
	  DTC [C] arch/arm64/boot/dts/qcom/ipq9574-rdp454.dtb
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dtb: usb@8af8800: interrupt-names: ['pwr_event'] is too short
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dtb: usb@8af8800: interrupts-extended: [[1, 0, 134, 4]] is too short
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dtb: usb@8af8800: interrupt-names: ['pwr_event'] is too short
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dtb: usb@8af8800: interrupts-extended: [[1, 0, 134, 4]] is too short
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dtb: usb@8af8800: interrupt-names: ['pwr_event'] is too short
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dtb: usb@8af8800: interrupts-extended: [[1, 0, 134, 4]] is too short
	Check:  arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dtb
	Check:  arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dtb: usb@8af8800: interrupt-names: ['pwr_event'] is too short
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dtb: usb@8af8800: interrupts-extended: [[1, 0, 134, 4]] is too short
	Check:  arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dtb: usb@8af8800: interrupt-names: ['pwr_event'] is too short
	/local/mnt/workspace/varada/upstream/pci-v10/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dtb: usb@8af8800: interrupts-extended: [[1, 0, 134, 4]] is too short
	Check:  arch/arm64/boot/dts/qcom/ipq9574-rdp418.dtb
	Check:  arch/arm64/boot/dts/qcom/ipq9574-rdp449.dtb
	Check:  arch/arm64/boot/dts/qcom/ipq9574-rdp453.dtb
	Check:  arch/arm64/boot/dts/qcom/ipq9574-rdp433.dtb
	Check:  arch/arm64/boot/dts/qcom/ipq9574-rdp454.dtb
Krzysztof Kozlowski Feb. 5, 2025, 3:53 p.m. UTC | #5 
On 05/02/2025 16:35, Varadarajan Narayanan wrote:
> On Wed, Feb 05, 2025 at 02:47:13PM +0100, Krzysztof Kozlowski wrote:
>> On 05/02/2025 11:49, Varadarajan Narayanan wrote:
>>> On Mon, Feb 03, 2025 at 05:30:32PM +0100, Krzysztof Kozlowski wrote:
>>>> On 28/01/2025 07:27, Varadarajan Narayanan wrote:
>>>>>
>>>>> @@ -479,6 +519,230 @@ frame@b128000 {
>>>>>  				status = "disabled";
>>>>>  			};
>>>>>  		};
>>>>> +
>>>>> +		pcie1: pcie@18000000 {
>>>>> +			compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
>>>>> +			reg = <0x00088000 0x3000>,
>>>>
>>>> So as Konrad pointed out now, this was never tested. It's not we who
>>>> should run tests for you. It's you.
>>>
>>> This was tested and it did not flag an error since it is having the order
>>> specified in the bindings. qcom,pcie.yaml has 4 reg specifications. Two of
>>
>>
>> Hm, then please paste results of dtbs_check W=1 testing. Here.
>>
>> I am 100% sure you have there warning and I don't understand your
>> reluctance to run the tests even after pointing it out by two people.
> 
> I ran the tests. Not sure which portions to paste. Have attached the full
> output just in case you are interested in some other detail. Please take a
> look.
> 
> Thanks
> Varada
> 
> 	$ grep ipq.*dtb dtbs-check.log

Where is the command you have used?

Best regards,
Krzysztof
Krzysztof Kozlowski Feb. 5, 2025, 3:54 p.m. UTC | #6 
On 05/02/2025 16:53, Krzysztof Kozlowski wrote:
> On 05/02/2025 16:35, Varadarajan Narayanan wrote:
>> On Wed, Feb 05, 2025 at 02:47:13PM +0100, Krzysztof Kozlowski wrote:
>>> On 05/02/2025 11:49, Varadarajan Narayanan wrote:
>>>> On Mon, Feb 03, 2025 at 05:30:32PM +0100, Krzysztof Kozlowski wrote:
>>>>> On 28/01/2025 07:27, Varadarajan Narayanan wrote:
>>>>>>
>>>>>> @@ -479,6 +519,230 @@ frame@b128000 {
>>>>>>  				status = "disabled";
>>>>>>  			};
>>>>>>  		};
>>>>>> +
>>>>>> +		pcie1: pcie@18000000 {
>>>>>> +			compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
>>>>>> +			reg = <0x00088000 0x3000>,
>>>>>
>>>>> So as Konrad pointed out now, this was never tested. It's not we who
>>>>> should run tests for you. It's you.
>>>>
>>>> This was tested and it did not flag an error since it is having the order
>>>> specified in the bindings. qcom,pcie.yaml has 4 reg specifications. Two of
>>>
>>>
>>> Hm, then please paste results of dtbs_check W=1 testing. Here.
>>>
>>> I am 100% sure you have there warning and I don't understand your
>>> reluctance to run the tests even after pointing it out by two people.
>>
>> I ran the tests. Not sure which portions to paste. Have attached the full
>> output just in case you are interested in some other detail. Please take a
>> look.
>>
>> Thanks
>> Varada
>>
>> 	$ grep ipq.*dtb dtbs-check.log
> 
> Where is the command you have used?


Although that might not matter - you skipped several warnings with your
grep. So maybe you need to fix your process, not sure.

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index ca3da95730bd..e5c920c21974 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -186,6 +186,46 @@  rng: rng@e3000 {
 			clock-names = "core";
 		};
 
+		pcie0_phy: phy@4b0000 {
+			compatible = "qcom,ipq5332-uniphy-pcie-phy";
+			reg = <0x004b0000 0x800>;
+
+			clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
+				 <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
+
+			resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
+				 <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
+				 <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
+
+			#clock-cells = <0>;
+
+			#phy-cells = <0>;
+
+			num-lanes = <1>;
+
+			status = "disabled";
+		};
+
+		pcie1_phy: phy@4b1000 {
+			compatible = "qcom,ipq5332-uniphy-pcie-phy";
+			reg = <0x004b1000 0x1000>;
+
+			clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>,
+				 <&gcc GCC_PCIE3X2_PHY_AHB_CLK>;
+
+			resets = <&gcc GCC_PCIE3X2_PHY_BCR>,
+				 <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>,
+				 <&gcc GCC_PCIE3X2PHY_PHY_BCR>;
+
+			#clock-cells = <0>;
+
+			#phy-cells = <0>;
+
+			num-lanes = <2>;
+
+			status = "disabled";
+		};
+
 		tlmm: pinctrl@1000000 {
 			compatible = "qcom,ipq5332-tlmm";
 			reg = <0x01000000 0x300000>;
@@ -212,8 +252,8 @@  gcc: clock-controller@1800000 {
 			#interconnect-cells = <1>;
 			clocks = <&xo_board>,
 				 <&sleep_clk>,
-				 <0>,
-				 <0>,
+				 <&pcie1_phy>,
+				 <&pcie0_phy>,
 				 <0>;
 		};
 
@@ -479,6 +519,230 @@  frame@b128000 {
 				status = "disabled";
 			};
 		};
+
+		pcie1: pcie@18000000 {
+			compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
+			reg = <0x00088000 0x3000>,
+			      <0x18000000 0xf1d>,
+			      <0x18000f20 0xa8>,
+			      <0x18001000 0x1000>,
+			      <0x18100000 0x1000>,
+			      <0x0008b000 0x1000>;
+			reg-names = "parf",
+				    "dbi",
+				    "elbi",
+				    "atu",
+				    "config",
+				    "mhi";
+			device_type = "pci";
+			linux,pci-domain = <1>;
+			num-lanes = <2>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x00100000>,
+				 <0x02000000 0x0 0x18300000 0x18300000 0x0 0x07d00000>;
+
+			msi-map = <0x0 &v2m0 0x0 0xffd>;
+
+			interrupts = <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7",
+					  "global";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 412 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 413 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 414 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 415 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_PCIE3X2_AXI_M_CLK>,
+				 <&gcc GCC_PCIE3X2_AXI_S_CLK>,
+				 <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
+				 <&gcc GCC_PCIE3X2_RCHG_CLK>,
+				 <&gcc GCC_PCIE3X2_AHB_CLK>,
+				 <&gcc GCC_PCIE3X2_AUX_CLK>;
+			clock-names = "axi_m",
+				      "axi_s",
+				      "axi_bridge",
+				      "rchng",
+				      "ahb",
+				      "aux";
+
+			assigned-clocks = <&gcc GCC_PCIE3X2_AUX_CLK>,
+					<&gcc GCC_PCIE3X2_AXI_M_CLK>,
+					<&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
+					<&gcc GCC_PCIE3X2_AXI_S_CLK>,
+					<&gcc GCC_PCIE3X2_RCHG_CLK>;
+
+			assigned-clock-rates = <2000000>,
+						<266666666>,
+						<240000000>,
+						<240000000>,
+						<100000000>;
+
+			resets = <&gcc GCC_PCIE3X2_PIPE_ARES>,
+				 <&gcc GCC_PCIE3X2_CORE_STICKY_ARES>,
+				 <&gcc GCC_PCIE3X2_AXI_S_STICKY_ARES>,
+				 <&gcc GCC_PCIE3X2_AXI_S_CLK_ARES>,
+				 <&gcc GCC_PCIE3X2_AXI_M_STICKY_ARES>,
+				 <&gcc GCC_PCIE3X2_AXI_M_CLK_ARES>,
+				 <&gcc GCC_PCIE3X2_AUX_CLK_ARES>,
+				 <&gcc GCC_PCIE3X2_AHB_CLK_ARES>;
+			reset-names = "pipe",
+				      "sticky",
+				      "axi_s_sticky",
+				      "axi_s",
+				      "axi_m_sticky",
+				      "axi_m",
+				      "aux",
+				      "ahb";
+
+			phys = <&pcie1_phy>;
+			phy-names = "pciephy";
+
+			interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>,
+					<&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+
+			status = "disabled";
+
+			pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+		};
+
+		pcie0: pcie@20000000 {
+			compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
+			reg = <0x00080000 0x3000>,
+			      <0x20000000 0xf1d>,
+			      <0x20000f20 0xa8>,
+			      <0x20001000 0x1000>,
+			      <0x20100000 0x1000>,
+			      <0x00083000 0x1000>;
+			reg-names = "parf",
+				    "dbi",
+				    "elbi",
+				    "atu",
+				    "config",
+				    "mhi";
+			device_type = "pci";
+			linux,pci-domain = <0>;
+			num-lanes = <1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x00100000>,
+				 <0x02000000 0x0 0x20300000 0x20300000 0x0 0x0fd00000>;
+
+			msi-map = <0x0 &v2m0 0x0 0xffd>;
+
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7",
+					  "global";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 36 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 37 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 38 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>,
+				 <&gcc GCC_PCIE3X1_0_AXI_S_CLK>,
+				 <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>,
+				 <&gcc GCC_PCIE3X1_0_RCHG_CLK>,
+				 <&gcc GCC_PCIE3X1_0_AHB_CLK>,
+				 <&gcc GCC_PCIE3X1_0_AUX_CLK>;
+			clock-names = "axi_m",
+				      "axi_s",
+				      "axi_bridge",
+				      "rchng",
+				      "ahb",
+				      "aux";
+
+			assigned-clocks = <&gcc GCC_PCIE3X1_0_AUX_CLK>,
+					<&gcc GCC_PCIE3X1_0_AXI_M_CLK>,
+					<&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>,
+					<&gcc GCC_PCIE3X1_0_AXI_S_CLK>,
+					<&gcc GCC_PCIE3X1_0_RCHG_CLK>;
+
+			assigned-clock-rates = <2000000>,
+						<240000000>,
+						<240000000>,
+						<240000000>,
+						<100000000>;
+
+			resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>,
+				 <&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>,
+				 <&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>,
+				 <&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>,
+				 <&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>,
+				 <&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>,
+				 <&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>,
+				 <&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>;
+			reset-names = "pipe",
+				      "sticky",
+				      "axi_s_sticky",
+				      "axi_s",
+				      "axi_m_sticky",
+				      "axi_m",
+				      "aux",
+				      "ahb";
+
+			phys = <&pcie0_phy>;
+			phy-names = "pciephy";
+
+			interconnects = <&gcc MASTER_SNOC_PCIE3_1_M &gcc SLAVE_SNOC_PCIE3_1_M>,
+					<&gcc MASTER_ANOC_PCIE3_1_S &gcc SLAVE_ANOC_PCIE3_1_S>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+
+			status = "disabled";
+
+			pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+		};
 	};
 
 	timer {