| Message ID | 20250214105007.97582-2-shradha.t@samsung.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | Add support for debugfs based RAS DES feature in PCIe DW | expand |
On Fri, Feb 14, 2025 at 04:20:04PM +0530, Shradha Todi wrote: > Add vendor specific extended configuration space capability search API > using struct dw_pcie pointer for DW controllers. > > Signed-off-by: Shradha Todi <shradha.t@samsung.com> I took this patch and modified to pass the 'struct dwc_pcie_vsec_id' to the API to simplify the callers: https://lore.kernel.org/linux-pci/20250218-pcie-qcom-ptm-v1-2-16d7e480d73e@linaro.org - Mani > --- > drivers/pci/controller/dwc/pcie-designware.c | 19 +++++++++++++++++++ > drivers/pci/controller/dwc/pcie-designware.h | 1 + > 2 files changed, 20 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 6d6cbc8b5b2c..3588197ba2d7 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -277,6 +277,25 @@ static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, > return 0; > } > > +u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id, u16 vsec_cap) > +{ > + u16 vsec = 0; > + u32 header; > + > + if (vendor_id != dw_pcie_readw_dbi(pci, PCI_VENDOR_ID)) > + return 0; > + > + while ((vsec = dw_pcie_find_next_ext_capability(pci, vsec, > + PCI_EXT_CAP_ID_VNDR))) { > + header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); > + if (PCI_VNDR_HEADER_ID(header) == vsec_cap) > + return vsec; > + } > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(dw_pcie_find_vsec_capability); > + > u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) > { > return dw_pcie_find_next_ext_capability(pci, 0, cap); > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 347ab74ac35a..02e94bd9b042 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -476,6 +476,7 @@ void dw_pcie_version_detect(struct dw_pcie *pci); > > u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); > u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); > +u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id, u16 vsec_cap); > > int dw_pcie_read(void __iomem *addr, int size, u32 *val); > int dw_pcie_write(void __iomem *addr, int size, u32 val); > -- > 2.17.1 >
> -----Original Message----- > From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > Sent: 18 February 2025 20:11 > To: Shradha Todi <shradha.t@samsung.com> > Cc: linux-kernel@vger.kernel.org; linux-pci@vger.kernel.org; lpieralisi@kernel.org; kw@linux.com; robh@kernel.org; > bhelgaas@google.com; jingoohan1@gmail.com; Jonathan.Cameron@Huawei.com; fan.ni@samsung.com; nifan.cxl@gmail.com; > a.manzanares@samsung.com; pankaj.dubey@samsung.com; cassel@kernel.org; 18255117159@163.com; > quic_nitegupt@quicinc.com; quic_krichai@quicinc.com; gost.dev@samsung.com > Subject: Re: [PATCH v6 1/4] PCI: dwc: Add support for vendor specific capability search > > On Fri, Feb 14, 2025 at 04:20:04PM +0530, Shradha Todi wrote: > > Add vendor specific extended configuration space capability search API > > using struct dw_pcie pointer for DW controllers. > > > > Signed-off-by: Shradha Todi <shradha.t@samsung.com> > > I took this patch and modified to pass the 'struct dwc_pcie_vsec_id' to the API to simplify the callers: > https://lore.kernel.org/linux-pci/20250218-pcie-qcom-ptm-v1-2-16d7e480d73e@linaro.org > > - Mani > I saw the series. I'm okay to move that to a common header file to avoid duplication but I feel that this movement will cause my patch to become dependent on your PTM series. Since that series in still in v1 stage and mine is already in v6, I feel the debugfs patchset will get further delayed. If you are okay, I could take in the changes as part of v7 after waiting for some more reviews. Or, the debugfs patches could be reviewed as it is, and the changes or movement could go on top of that? > > --- > > drivers/pci/controller/dwc/pcie-designware.c | 19 +++++++++++++++++++ > > drivers/pci/controller/dwc/pcie-designware.h | 1 + > > 2 files changed, 20 insertions(+) > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c > > b/drivers/pci/controller/dwc/pcie-designware.c > > index 6d6cbc8b5b2c..3588197ba2d7 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > @@ -277,6 +277,25 @@ static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, > > return 0; > > } > > > > +u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id, > > +u16 vsec_cap) { > > + u16 vsec = 0; > > + u32 header; > > + > > + if (vendor_id != dw_pcie_readw_dbi(pci, PCI_VENDOR_ID)) > > + return 0; > > + > > + while ((vsec = dw_pcie_find_next_ext_capability(pci, vsec, > > + PCI_EXT_CAP_ID_VNDR))) { > > + header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); > > + if (PCI_VNDR_HEADER_ID(header) == vsec_cap) > > + return vsec; > > + } > > + > > + return 0; > > +} > > +EXPORT_SYMBOL_GPL(dw_pcie_find_vsec_capability); > > + > > u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) { > > return dw_pcie_find_next_ext_capability(pci, 0, cap); diff --git > > a/drivers/pci/controller/dwc/pcie-designware.h > > b/drivers/pci/controller/dwc/pcie-designware.h > > index 347ab74ac35a..02e94bd9b042 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.h > > +++ b/drivers/pci/controller/dwc/pcie-designware.h > > @@ -476,6 +476,7 @@ void dw_pcie_version_detect(struct dw_pcie *pci); > > > > u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); > > u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); > > +u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id, > > +u16 vsec_cap); > > > > int dw_pcie_read(void __iomem *addr, int size, u32 *val); int > > dw_pcie_write(void __iomem *addr, int size, u32 val); > > -- > > 2.17.1 > > > > -- > மணிவண்ணன் சதாசிவம்
On Thu, Feb 20, 2025 at 11:44:36AM +0530, Shradha Todi wrote: > > > > -----Original Message----- > > From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > Sent: 18 February 2025 20:11 > > To: Shradha Todi <shradha.t@samsung.com> > > Cc: linux-kernel@vger.kernel.org; linux-pci@vger.kernel.org; lpieralisi@kernel.org; kw@linux.com; robh@kernel.org; > > bhelgaas@google.com; jingoohan1@gmail.com; Jonathan.Cameron@Huawei.com; fan.ni@samsung.com; nifan.cxl@gmail.com; > > a.manzanares@samsung.com; pankaj.dubey@samsung.com; cassel@kernel.org; 18255117159@163.com; > > quic_nitegupt@quicinc.com; quic_krichai@quicinc.com; gost.dev@samsung.com > > Subject: Re: [PATCH v6 1/4] PCI: dwc: Add support for vendor specific capability search > > > > On Fri, Feb 14, 2025 at 04:20:04PM +0530, Shradha Todi wrote: > > > Add vendor specific extended configuration space capability search API > > > using struct dw_pcie pointer for DW controllers. > > > > > > Signed-off-by: Shradha Todi <shradha.t@samsung.com> > > > > I took this patch and modified to pass the 'struct dwc_pcie_vsec_id' to the API to simplify the callers: > > https://lore.kernel.org/linux-pci/20250218-pcie-qcom-ptm-v1-2-16d7e480d73e@linaro.org > > > > - Mani > > > > I saw the series. I'm okay to move that to a common header file to avoid duplication but I feel that this movement will > cause my patch to become dependent on your PTM series. Since that series in still in v1 stage and mine is already in v6, > I feel the debugfs patchset will get further delayed. If you are okay, I could take in the changes as part of v7 after waiting > for some more reviews. Or, the debugfs patches could be reviewed as it is, and the changes or movement could go on top > of that? > You can take my first 2 patches. I'll post my v2 on top of your next version. - Mani
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 6d6cbc8b5b2c..3588197ba2d7 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -277,6 +277,25 @@ static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, return 0; } +u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id, u16 vsec_cap) +{ + u16 vsec = 0; + u32 header; + + if (vendor_id != dw_pcie_readw_dbi(pci, PCI_VENDOR_ID)) + return 0; + + while ((vsec = dw_pcie_find_next_ext_capability(pci, vsec, + PCI_EXT_CAP_ID_VNDR))) { + header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); + if (PCI_VNDR_HEADER_ID(header) == vsec_cap) + return vsec; + } + + return 0; +} +EXPORT_SYMBOL_GPL(dw_pcie_find_vsec_capability); + u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) { return dw_pcie_find_next_ext_capability(pci, 0, cap); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 347ab74ac35a..02e94bd9b042 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -476,6 +476,7 @@ void dw_pcie_version_detect(struct dw_pcie *pci); u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); +u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, u16 vendor_id, u16 vsec_cap); int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val);
Add vendor specific extended configuration space capability search API using struct dw_pcie pointer for DW controllers. Signed-off-by: Shradha Todi <shradha.t@samsung.com> --- drivers/pci/controller/dwc/pcie-designware.c | 19 +++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 20 insertions(+)