| Message ID | 20250221-sar2130p-pci-v3-1-61a0fdfb75b4@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | PCI: qcom-ep: add support for using the EP on SAR2130P and SM8450 | expand |
On Fri, Feb 21, 2025 at 05:51:59PM +0200, Dmitry Baryshkov wrote: > Qualcomm SA8775P supports cache coherency on the PCIe EP controller. > Allow 'dma-coherent' property to be used for this device. This fixes > a part of the following error (the second part is fixed in the next > commit): > > pcie-ep@1c10000: Unevaluated properties are not allowed ('dma-coherent', 'iommus' were unexpected) > > Fixes: 4b220c6fa9f3 ("arm64: dts: qcom: sa8775p: Mark PCIe EP controller as cache coherent") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Fri, Feb 21, 2025 at 05:51:59PM +0200, Dmitry Baryshkov wrote: > Qualcomm SA8775P supports cache coherency on the PCIe EP controller. > Allow 'dma-coherent' property to be used for this device. This fixes > a part of the following error (the second part is fixed in the next > commit): > > pcie-ep@1c10000: Unevaluated properties are not allowed ('dma-coherent', 'iommus' were unexpected) > > Fixes: 4b220c6fa9f3 ("arm64: dts: qcom: sa8775p: Mark PCIe EP controller as cache coherent") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > index 1226ee5d08d1ae909b07b0d78014618c4c74e9a8..0c2ca4cfa3b190b3fb204f0d7142370734fb3534 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > @@ -91,6 +91,8 @@ properties: > - const: pcie-mem > - const: cpu-pcie > > + dma-coherent: true > + > resets: > maxItems: 1 > > > -- > 2.39.5 >
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 1226ee5d08d1ae909b07b0d78014618c4c74e9a8..0c2ca4cfa3b190b3fb204f0d7142370734fb3534 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -91,6 +91,8 @@ properties: - const: pcie-mem - const: cpu-pcie + dma-coherent: true + resets: maxItems: 1
Qualcomm SA8775P supports cache coherency on the PCIe EP controller. Allow 'dma-coherent' property to be used for this device. This fixes a part of the following error (the second part is fixed in the next commit): pcie-ep@1c10000: Unevaluated properties are not allowed ('dma-coherent', 'iommus' were unexpected) Fixes: 4b220c6fa9f3 ("arm64: dts: qcom: sa8775p: Mark PCIe EP controller as cache coherent") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++ 1 file changed, 2 insertions(+)