| Message ID | 20250415072724.3565533-10-peter.chen@cixtech.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: Introduce CIX P1 (SKY1) SoC | expand |
On Tue, Apr 15, 2025 at 03:27:23PM +0800, Peter Chen wrote: > CIX SKY1 SoC is high performance Armv9 SoC designed by Cixtech, > and Orion O6 is the motherboard launched by Radxa. See below for > detail: > https://docs.radxa.com/en/orion/o6/getting-started/introduction > In this commit, it adds sky1 base, mailbox, clock (scmi firmware baseed) > and uart, and the kernel could boot up to console. The commit message style is supposed to be in imperative tone, i.e. "Add sky1 base". > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Acked-by: Fugang Duan <fugang.duan@cixtech.com> > Signed-off-by: Guomin Chen <Guomin.Chen@cixtech.com> > Signed-off-by: Gary Yang <gary.yang@cixtech.com> > Signed-off-by: Peter Chen <peter.chen@cixtech.com> > --- I've tested this on my own Orion O6 with 6.15-rc2, the UART does work and the kernel does boot up to the expected point. Feel free to add the tag if you'd like. Tested-by: Kajetan Puchalski <kajetan.puchalski@arm.com> > +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts > @@ -0,0 +1,39 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright 2025 Cix Technology Group Co., Ltd. > + * > + */ > + > +/dts-v1/; > + > +#include "sky1.dtsi" > +/ { > + model = "Radxa Orion O6"; > + compatible = "radxa,orion-o6", "cix,sky1"; > + > + aliases { > + serial2 = &uart2; > + }; > + > + chosen { > + stdout-path = &uart2; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + linux,cma { > + compatible = "shared-dma-pool"; > + reusable; > + size = <0x0 0x28000000>; > + linux,cma-default; > + }; > + }; > + > +}; > + > +&uart2 { > + status = "okay"; > +};
On 25-04-15 13:48:38, Kajetan Puchalski wrote: > > On Tue, Apr 15, 2025 at 03:27:23PM +0800, Peter Chen wrote: > > CIX SKY1 SoC is high performance Armv9 SoC designed by Cixtech, > > and Orion O6 is the motherboard launched by Radxa. See below for > > detail: > > https://docs.radxa.com/en/orion/o6/getting-started/introduction > > In this commit, it adds sky1 base, mailbox, clock (scmi firmware baseed) > > and uart, and the kernel could boot up to console. > > The commit message style is supposed to be in imperative tone, i.e. "Add sky1 base". Thanks, I will change subject to "arm64: dts: cix: Add sky1 base dts initial support" > > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > Acked-by: Fugang Duan <fugang.duan@cixtech.com> > > Signed-off-by: Guomin Chen <Guomin.Chen@cixtech.com> > > Signed-off-by: Gary Yang <gary.yang@cixtech.com> > > Signed-off-by: Peter Chen <peter.chen@cixtech.com> > > --- > > I've tested this on my own Orion O6 with 6.15-rc2, the UART does work and the kernel > does boot up to the expected point. Feel free to add the tag if you'd like. > > Tested-by: Kajetan Puchalski <kajetan.puchalski@arm.com> Thanks for your testing. Peter
On 15/04/2025 09:27, Peter Chen wrote: > + > + mbox_ap2pm: mailbox@6590080 { > + compatible = "cix,sky1-mbox"; > + reg = <0x0 0x06590080 0x0 0xff80>; > + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; > + #mbox-cells = <1>; > + cix,mbox-dir = "tx"; > + }; > + > + pm2ap_scmi_mem: pm2ap-shmem@65a0000 { > + compatible = "arm,scmi-shmem"; > + #address-cells = <2>; > + #size-cells = <2>; > + reg-io-width = <4>; > + reg = <0x0 0x065a0000 0x0 0x80>; Messed order of properties. Keep it consistent (see DTS conding style). Other nodes also have oddly placed reg. Best regards, Krzysztof
On 15/04/2025 09:27, Peter Chen wrote: > CIX SKY1 SoC is high performance Armv9 SoC designed by Cixtech, > and Orion O6 is the motherboard launched by Radxa. See below for > detail: > https://docs.radxa.com/en/orion/o6/getting-started/introduction > > In this commit, it adds sky1 base, mailbox, clock (scmi firmware baseed) > and uart, and the kernel could boot up to console. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> You added several new device nodes, so obviously this is not true anymore. This is explained in submitting patches - you must drop the review when making substantial changes. Adding several nodes is a substantial change. > Acked-by: Fugang Duan <fugang.duan@cixtech.com> And this as well Best regards, Krzysztof
On 25-04-17 08:18:44, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL > > On 15/04/2025 09:27, Peter Chen wrote: > > + > > + mbox_ap2pm: mailbox@6590080 { > > + compatible = "cix,sky1-mbox"; > > + reg = <0x0 0x06590080 0x0 0xff80>; > > + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; > > + #mbox-cells = <1>; > > + cix,mbox-dir = "tx"; > > + }; > > + > > + pm2ap_scmi_mem: pm2ap-shmem@65a0000 { > > + compatible = "arm,scmi-shmem"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + reg-io-width = <4>; > > + reg = <0x0 0x065a0000 0x0 0x80>; > > Messed order of properties. Keep it consistent (see DTS conding style). > Other nodes also have oddly placed reg. Thanks for your reviewing, Krzysztof. All the nodes mailbox and shmem (in mailbox) are on the same bus, so I keep it by unit address in ascending order like DTS coding sytle says. I think below rules are two options, isn't it? 1. Nodes on any bus, thus using unit addresses for children, shall be ordered by unit address in ascending order. Alternatively for some subarchitectures, nodes of the same type can be grouped together, e.g. all I2C controllers one after another even if this breaks unit address ordering. > > > > Best regards, > Krzysztof
On 25-04-17 08:19:59, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL > > On 15/04/2025 09:27, Peter Chen wrote: > > CIX SKY1 SoC is high performance Armv9 SoC designed by Cixtech, > > and Orion O6 is the motherboard launched by Radxa. See below for > > detail: > > https://docs.radxa.com/en/orion/o6/getting-started/introduction > > > > In this commit, it adds sky1 base, mailbox, clock (scmi firmware baseed) > > and uart, and the kernel could boot up to console. > > > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > You added several new device nodes, so obviously this is not true anymore. > > This is explained in submitting patches - you must drop the review when > making substantial changes. Adding several nodes is a substantial change. > > > Acked-by: Fugang Duan <fugang.duan@cixtech.com> > > And this as well Okay, I will delete both tags for the next submission.
On 17/04/2025 08:37, Peter Chen wrote: > On 25-04-17 08:18:44, Krzysztof Kozlowski wrote: >> EXTERNAL EMAIL >> >> On 15/04/2025 09:27, Peter Chen wrote: >>> + >>> + mbox_ap2pm: mailbox@6590080 { >>> + compatible = "cix,sky1-mbox"; >>> + reg = <0x0 0x06590080 0x0 0xff80>; >>> + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; >>> + #mbox-cells = <1>; >>> + cix,mbox-dir = "tx"; >>> + }; >>> + >>> + pm2ap_scmi_mem: pm2ap-shmem@65a0000 { >>> + compatible = "arm,scmi-shmem"; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + reg-io-width = <4>; >>> + reg = <0x0 0x065a0000 0x0 0x80>; >> >> Messed order of properties. Keep it consistent (see DTS conding style). >> Other nodes also have oddly placed reg. > > Thanks for your reviewing, Krzysztof. > > All the nodes mailbox and shmem (in mailbox) are on the same bus, so > I keep it by unit address in ascending order like DTS coding sytle > says. I think below rules are two options, isn't it? You speak about nodes I wrote about properties. I don't understand how your question is relevant to my comment. Best regards, Krzysztof
> >> > >> On 15/04/2025 09:27, Peter Chen wrote: > >>> + > >>> + mbox_ap2pm: mailbox@6590080 { > >>> + compatible = "cix,sky1-mbox"; > >>> + reg = <0x0 0x06590080 0x0 0xff80>; > >>> + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; > >>> + #mbox-cells = <1>; > >>> + cix,mbox-dir = "tx"; > >>> + }; > >>> + > >>> + pm2ap_scmi_mem: pm2ap-shmem@65a0000 { > >>> + compatible = "arm,scmi-shmem"; > >>> + #address-cells = <2>; > >>> + #size-cells = <2>; > >>> + reg-io-width = <4>; > >>> + reg = <0x0 0x065a0000 0x0 0x80>; > >> > >> Messed order of properties. Keep it consistent (see DTS conding style). > >> Other nodes also have oddly placed reg. > > > > Thanks for your reviewing, Krzysztof. > > > > All the nodes mailbox and shmem (in mailbox) are on the same bus, so > > I keep it by unit address in ascending order like DTS coding sytle > > says. I think below rules are two options, isn't it? > > You speak about nodes I wrote about properties. I don't understand how > your question is relevant to my comment. > > Sorry, we will update the sequence of properties in node.
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 79b73a21ddc2..8e7ccd0027bd 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -13,6 +13,7 @@ subdir-y += bitmain subdir-y += blaize subdir-y += broadcom subdir-y += cavium +subdir-y += cix subdir-y += exynos subdir-y += freescale subdir-y += hisilicon diff --git a/arch/arm64/boot/dts/cix/Makefile b/arch/arm64/boot/dts/cix/Makefile new file mode 100644 index 000000000000..ed3713982012 --- /dev/null +++ b/arch/arm64/boot/dts/cix/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_CIX) += sky1-orion-o6.dtb diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts new file mode 100644 index 000000000000..d74964d53c3b --- /dev/null +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 Cix Technology Group Co., Ltd. + * + */ + +/dts-v1/; + +#include "sky1.dtsi" +/ { + model = "Radxa Orion O6"; + compatible = "radxa,orion-o6", "cix,sky1"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = &uart2; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x28000000>; + linux,cma-default; + }; + }; + +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi new file mode 100644 index 000000000000..11816b52462b --- /dev/null +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 Cix Technology Group Co., Ltd. + * + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sky1-clk.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a520"; + enable-method = "psci"; + reg = <0x0 0x0>; + device_type = "cpu"; + capacity-dmips-mhz = <403>; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a520"; + enable-method = "psci"; + reg = <0x0 0x100>; + device_type = "cpu"; + capacity-dmips-mhz = <403>; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a520"; + enable-method = "psci"; + reg = <0x0 0x200>; + device_type = "cpu"; + capacity-dmips-mhz = <403>; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a520"; + enable-method = "psci"; + reg = <0x0 0x300>; + device_type = "cpu"; + capacity-dmips-mhz = <403>; + }; + + cpu4: cpu@400 { + compatible = "arm,cortex-a720"; + enable-method = "psci"; + reg = <0x0 0x400>; + device_type = "cpu"; + capacity-dmips-mhz = <1024>; + }; + + cpu5: cpu@500 { + compatible = "arm,cortex-a720"; + enable-method = "psci"; + reg = <0x0 0x500>; + device_type = "cpu"; + capacity-dmips-mhz = <1024>; + }; + + cpu6: cpu@600 { + compatible = "arm,cortex-a720"; + enable-method = "psci"; + reg = <0x0 0x600>; + device_type = "cpu"; + capacity-dmips-mhz = <1024>; + }; + + cpu7: cpu@700 { + compatible = "arm,cortex-a720"; + enable-method = "psci"; + reg = <0x0 0x700>; + device_type = "cpu"; + capacity-dmips-mhz = <1024>; + }; + + cpu8: cpu@800 { + compatible = "arm,cortex-a720"; + enable-method = "psci"; + reg = <0x0 0x800>; + device_type = "cpu"; + capacity-dmips-mhz = <1024>; + }; + + cpu9: cpu@900 { + compatible = "arm,cortex-a720"; + enable-method = "psci"; + reg = <0x0 0x900>; + device_type = "cpu"; + capacity-dmips-mhz = <1024>; + }; + + cpu10: cpu@a00 { + compatible = "arm,cortex-a720"; + enable-method = "psci"; + reg = <0x0 0xa00>; + device_type = "cpu"; + capacity-dmips-mhz = <1024>; + }; + + cpu11: cpu@b00 { + compatible = "arm,cortex-a720"; + enable-method = "psci"; + reg = <0x0 0xb00>; + device_type = "cpu"; + capacity-dmips-mhz = <1024>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + core4 { + cpu = <&cpu4>; + }; + core5 { + cpu = <&cpu5>; + }; + core6 { + cpu = <&cpu6>; + }; + core7 { + cpu = <&cpu7>; + }; + core8 { + cpu = <&cpu8>; + }; + core9 { + cpu = <&cpu9>; + }; + core10 { + cpu = <&cpu10>; + }; + core11 { + cpu = <&cpu11>; + }; + }; + }; + }; + + firmware { + ap_to_pm_scmi: scmi { + compatible = "arm,scmi"; + mbox-names = "tx", "rx"; + mboxes = <&mbox_ap2pm 8>, <&mbox_pm2ap 8>; + shmem = <&ap2pm_scmi_mem &pm2ap_scmi_mem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + }; + }; + + pmu-a520 { + compatible = "arm,cortex-a520-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>; + }; + + pmu-a720 { + compatible = "arm,cortex-a720-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc@0 { + compatible = "simple-bus"; + ranges = <0 0 0 0 0x20 0>; + dma-ranges; + #address-cells = <2>; + #size-cells = <2>; + + uart0: serial@40b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x040b0000 0x0 0x1000>; + interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&scmi_clk CLK_TREE_FCH_UART0_FUNC>, <&scmi_clk CLK_TREE_FCH_UART0_APB>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart1: serial@40c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x040c0000 0x0 0x1000>; + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&scmi_clk CLK_TREE_FCH_UART1_FUNC>, <&scmi_clk CLK_TREE_FCH_UART1_APB>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart2: serial@40d0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x040d0000 0x0 0x1000>; + interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&scmi_clk CLK_TREE_FCH_UART2_FUNC>, <&scmi_clk CLK_TREE_FCH_UART2_APB>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart3: serial@40e0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x040e0000 0x0 0x1000>; + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&scmi_clk CLK_TREE_FCH_UART3_FUNC>, <&scmi_clk CLK_TREE_FCH_UART3_APB>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + mbox_ap2se: mailbox@5060000 { + compatible = "cix,sky1-mbox"; + reg = <0x0 0x05060000 0x0 0x10000>; + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <1>; + cix,mbox-dir = "tx"; + }; + + mbox_se2ap: mailbox@5070000 { + compatible = "cix,sky1-mbox"; + reg = <0x0 0x05070000 0x0 0x10000>; + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <1>; + cix,mbox-dir = "rx"; + }; + + ap2pm_scmi_mem: ap2pm-shmem@6590000 { + compatible = "arm,scmi-shmem"; + #address-cells = <2>; + #size-cells = <2>; + reg-io-width = <4>; + reg = <0x0 0x06590000 0x0 0x80>; + }; + + mbox_ap2pm: mailbox@6590080 { + compatible = "cix,sky1-mbox"; + reg = <0x0 0x06590080 0x0 0xff80>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <1>; + cix,mbox-dir = "tx"; + }; + + pm2ap_scmi_mem: pm2ap-shmem@65a0000 { + compatible = "arm,scmi-shmem"; + #address-cells = <2>; + #size-cells = <2>; + reg-io-width = <4>; + reg = <0x0 0x065a0000 0x0 0x80>; + }; + + mbox_pm2ap: mailbox@65a0080 { + compatible = "cix,sky1-mbox"; + reg = <0x0 0x065a0080 0x0 0xff80>; + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <1>; + cix,mbox-dir = "rx"; + }; + + mbox_sfh2ap: mailbox@8090000 { + compatible = "cix,sky1-mbox"; + reg = <0x0 0x08090000 0x0 0x10000>; + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <1>; + cix,mbox-dir = "rx"; + }; + + mbox_ap2sfh: mailbox@80a0000 { + compatible = "cix,sky1-mbox"; + reg = <0x0 0x080a0000 0x0 0x10000>; + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <1>; + cix,mbox-dir = "tx"; + }; + + gic: interrupt-controller@e010000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x0e010000 0 0x10000>, /* GICD */ + <0x0 0x0e090000 0 0x300000>; /* GICR * 12 */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>; + #interrupt-cells = <4>; + interrupt-controller; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic_its: msi-controller@e050000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x0e050000 0x0 0x30000>; + msi-controller; + #msi-cells = <1>; + }; + + ppi-partitions { + ppi_partition0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + + ppi_partition1: interrupt-partition-1 { + affinity = <&cpu4 &cpu5 &cpu6 &cpu7 &cpu8 &cpu9 &cpu10 &cpu11>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>; + }; +};