| Message ID | 1352911659-11757-1-git-send-email-daniel.vetter@ffwll.ch (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, 14 Nov 2012 17:47:39 +0100, Daniel Vetter <daniel.vetter@ffwll.ch> wrote: > Jani Nikula noticed that the parentheses are wrong and we & the bit > with the register address instead of the read-back value. He sent a > patch to correct that. > > On second look, we write the same register in the previous line, and > the w/a seems to be to set FDI_RX_PHASE_SYNC_POINTER_OVR to enable the > logic, then keep always set FDI_RX_PHASE_SYNC_POINTER_OVR and toggle > ~FDI_RX_PHASE_SYNC_POINTER_EN before/after enabling the pc transcoder. > > So the right things seems to be to simply kill the 2nd write. > > Cc: Jani Nikula <jani.nikula@intel.com> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Looks sane(r). Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
On Thu, Nov 15, 2012 at 10:42:02AM +0000, Chris Wilson wrote: > On Wed, 14 Nov 2012 17:47:39 +0100, Daniel Vetter <daniel.vetter@ffwll.ch> wrote: > > Jani Nikula noticed that the parentheses are wrong and we & the bit > > with the register address instead of the read-back value. He sent a > > patch to correct that. > > > > On second look, we write the same register in the previous line, and > > the w/a seems to be to set FDI_RX_PHASE_SYNC_POINTER_OVR to enable the > > logic, then keep always set FDI_RX_PHASE_SYNC_POINTER_OVR and toggle > > ~FDI_RX_PHASE_SYNC_POINTER_EN before/after enabling the pc transcoder. > > > > So the right things seems to be to simply kill the 2nd write. > > > > Cc: Jani Nikula <jani.nikula@intel.com> > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> > > Looks sane(r). > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Queued for -next, thanks for the review. -Daniel
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f95d537..ed79e51 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2924,9 +2924,6 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc) /* Ironlake workaround, disable clock pointer after downing FDI */ if (HAS_PCH_IBX(dev)) { I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); - I915_WRITE(FDI_RX_CHICKEN(pipe), - I915_READ(FDI_RX_CHICKEN(pipe) & - ~FDI_RX_PHASE_SYNC_POINTER_EN)); } else if (HAS_PCH_CPT(dev)) { cpt_phase_pointer_disable(dev, pipe); }
Jani Nikula noticed that the parentheses are wrong and we & the bit with the register address instead of the read-back value. He sent a patch to correct that. On second look, we write the same register in the previous line, and the w/a seems to be to set FDI_RX_PHASE_SYNC_POINTER_OVR to enable the logic, then keep always set FDI_RX_PHASE_SYNC_POINTER_OVR and toggle ~FDI_RX_PHASE_SYNC_POINTER_EN before/after enabling the pc transcoder. So the right things seems to be to simply kill the 2nd write. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/intel_display.c | 3 --- 1 file changed, 3 deletions(-)