diff mbox

ssb: implement ssb spuravoid for chipid BCM43222

Message ID 1365684013-3483-1-git-send-email-hauke@hauke-m.de (mailing list archive)
State Not Applicable, archived
Headers show

Commit Message

Hauke Mehrtens April 11, 2013, 12:40 p.m. UTC
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 drivers/ssb/driver_chipcommon_pmu.c |   19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

Comments

Rafał Miłecki April 12, 2013, 6:29 a.m. UTC | #1
2013/4/11 Hauke Mehrtens <hauke@hauke-m.de>:
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

Ack
Hauke Mehrtens April 24, 2013, 5:29 p.m. UTC | #2
On 04/12/2013 08:29 AM, Rafa? Mi?ecki wrote:
> 2013/4/11 Hauke Mehrtens <hauke@hauke-m.de>:
>> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> 
> Ack
> 
Hi John,

is there any problem with this patch?

Hauke
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John W. Linville April 24, 2013, 5:33 p.m. UTC | #3
On Wed, Apr 24, 2013 at 07:29:21PM +0200, Hauke Mehrtens wrote:
> On 04/12/2013 08:29 AM, Rafa? Mi?ecki wrote:
> > 2013/4/11 Hauke Mehrtens <hauke@hauke-m.de>:
> >> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> > 
> > Ack
> > 
> Hi John,
> 
> is there any problem with this patch?
> 
> Hauke

Sorry, I haven't been able to get it to apply.  Could you rebase it?
diff mbox

Patch

diff --git a/drivers/ssb/driver_chipcommon_pmu.c b/drivers/ssb/driver_chipcommon_pmu.c
index 23c5dbf..1173a09 100644
--- a/drivers/ssb/driver_chipcommon_pmu.c
+++ b/drivers/ssb/driver_chipcommon_pmu.c
@@ -687,8 +687,23 @@  void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
 		pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
 		break;
 	case 43222:
-		/* TODO: BCM43222 requires updating PLLs too */
-		return;
+		if (spuravoid == 1) {
+			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008);
+			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06);
+			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08);
+			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
+			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920);
+			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815);
+		} else {
+			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008);
+			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06);
+			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08);
+			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
+			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0);
+			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855);
+		}
+		pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
+		break;
 	default:
 		ssb_printk(KERN_ERR PFX
 			   "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",