diff mbox

[Query/Discussion] : IO translation with designware PCIe controller

Message ID 001101cef5f6$4347c520$c9d74f60$%han@samsung.com (mailing list archive)
State New, archived
Delegated to: Bjorn Helgaas
Headers show

Commit Message

Jingoo Han Dec. 10, 2013, 10:22 p.m. UTC 
On Tuesday, December 10, 2013 10:27 PM, Marek Vasut wrote:
> On Monday, December 09, 2013 at 08:12:42 AM, Pratyush Anand wrote:

[.....]

> >
> > diff --git a/drivers/pci/host/pcie-designware.c
> > b/drivers/pci/host/pcie-designware.c index be6ce30..cf68632 100644
> > --- a/drivers/pci/host/pcie-designware.c
> > +++ b/drivers/pci/host/pcie-designware.c
> > @@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >  					   + global_io_offset);
> >  			pp->config.io_size = resource_size(&pp->io);
> >  			pp->config.io_bus_addr = range.pci_addr;
> > +			pp->io_base = range.cpu_addr;
> >  		}
> >  		if (restype == IORESOURCE_MEM) {
> >  			of_pci_range_to_resource(&range, np, &pp->mem);
> > @@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >
> >  	pp->cfg0_base = pp->cfg.start;
> >  	pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
> > -	pp->io_base = pp->io.start;
> >  	pp->mem_base = pp->mem.start;
> >
> >  	pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
> > @@ -667,7 +667,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data
> > *sys)
> >
> >  	if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
> >  		sys->io_offset = global_io_offset - pp->config.io_bus_addr;
> > -		pci_ioremap_io(sys->io_offset, pp->io.start);
> > +		pci_ioremap_io(sys->io_offset, pp->io_base);
> >  		global_io_offset += SZ_64K;
> >  		pci_add_resource_offset(&sys->resources, &pp->io,
> >  					sys->io_offset);
> 
> Tim, can you test if this patch fixes your SKY2 IOspace problem please ?

Above mentioned patch is NOT the latest patch.
Pratyush Anand already submitted the next patch as below.

Tim,
Would you test the following patch on i.MX6 platform?



Best regards,
Jingoo Han

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Comments

Tim Harvey Dec. 10, 2013, 11:23 p.m. UTC | #1 
On Tue, Dec 10, 2013 at 2:22 PM, Jingoo Han <jg1.han@samsung.com> wrote:
> On Tuesday, December 10, 2013 10:27 PM, Marek Vasut wrote:
>> On Monday, December 09, 2013 at 08:12:42 AM, Pratyush Anand wrote:
>
> [.....]
>
>> >
>> > diff --git a/drivers/pci/host/pcie-designware.c
>> > b/drivers/pci/host/pcie-designware.c index be6ce30..cf68632 100644
>> > --- a/drivers/pci/host/pcie-designware.c
>> > +++ b/drivers/pci/host/pcie-designware.c
>> > @@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>> >                                        + global_io_offset);
>> >                     pp->config.io_size = resource_size(&pp->io);
>> >                     pp->config.io_bus_addr = range.pci_addr;
>> > +                   pp->io_base = range.cpu_addr;
>> >             }
>> >             if (restype == IORESOURCE_MEM) {
>> >                     of_pci_range_to_resource(&range, np, &pp->mem);
>> > @@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>> >
>> >     pp->cfg0_base = pp->cfg.start;
>> >     pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
>> > -   pp->io_base = pp->io.start;
>> >     pp->mem_base = pp->mem.start;
>> >
>> >     pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
>> > @@ -667,7 +667,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data
>> > *sys)
>> >
>> >     if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
>> >             sys->io_offset = global_io_offset - pp->config.io_bus_addr;
>> > -           pci_ioremap_io(sys->io_offset, pp->io.start);
>> > +           pci_ioremap_io(sys->io_offset, pp->io_base);
>> >             global_io_offset += SZ_64K;
>> >             pci_add_resource_offset(&sys->resources, &pp->io,
>> >                                     sys->io_offset);
>>
>> Tim, can you test if this patch fixes your SKY2 IOspace problem please ?
>
> Above mentioned patch is NOT the latest patch.
> Pratyush Anand already submitted the next patch as below.
>
> Tim,
> Would you test the following patch on i.MX6 platform?
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index be6ce30..b83f5e8 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>                                            + global_io_offset);
>                         pp->config.io_size = resource_size(&pp->io);
>                         pp->config.io_bus_addr = range.pci_addr;
> +                       pp->io_base = range.cpu_addr;
>                 }
>                 if (restype == IORESOURCE_MEM) {
>                         of_pci_range_to_resource(&range, np, &pp->mem);
> @@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>
>         pp->cfg0_base = pp->cfg.start;
>         pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
> -       pp->io_base = pp->io.start;
>         pp->mem_base = pp->mem.start;
>
>         pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
> @@ -667,7 +667,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
>
>         if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
>                 sys->io_offset = global_io_offset - pp->config.io_bus_addr;
> -               pci_ioremap_io(sys->io_offset, pp->io.start);
> +               pci_ioremap_io(global_io_offset, pp->io_base);
>                 global_io_offset += SZ_64K;
>                 pci_add_resource_offset(&sys->resources, &pp->io,
>                                         sys->io_offset);
>
>
> Best regards,
> Jingoo Han
>

Yes, this patch resolves the issue and now I can use devices with io
resources behind a bridge attached to the IMX6.

Thanks everyone for your efforts!

Tim
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Marek Vasut Dec. 10, 2013, 11:25 p.m. UTC | #2 
On Wednesday, December 11, 2013 at 12:23:47 AM, Tim Harvey wrote:
> On Tue, Dec 10, 2013 at 2:22 PM, Jingoo Han <jg1.han@samsung.com> wrote:
> > On Tuesday, December 10, 2013 10:27 PM, Marek Vasut wrote:
> >> On Monday, December 09, 2013 at 08:12:42 AM, Pratyush Anand wrote:
> > [.....]
> > 
> >> > diff --git a/drivers/pci/host/pcie-designware.c
> >> > b/drivers/pci/host/pcie-designware.c index be6ce30..cf68632 100644
> >> > --- a/drivers/pci/host/pcie-designware.c
> >> > +++ b/drivers/pci/host/pcie-designware.c
> >> > @@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >> > 
> >> >                                        + global_io_offset);
> >> >                     
> >> >                     pp->config.io_size = resource_size(&pp->io);
> >> >                     pp->config.io_bus_addr = range.pci_addr;
> >> > 
> >> > +                   pp->io_base = range.cpu_addr;
> >> > 
> >> >             }
> >> >             if (restype == IORESOURCE_MEM) {
> >> >             
> >> >                     of_pci_range_to_resource(&range, np, &pp->mem);
> >> > 
> >> > @@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >> > 
> >> >     pp->cfg0_base = pp->cfg.start;
> >> >     pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
> >> > 
> >> > -   pp->io_base = pp->io.start;
> >> > 
> >> >     pp->mem_base = pp->mem.start;
> >> >     
> >> >     pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
> >> > 
> >> > @@ -667,7 +667,7 @@ static int dw_pcie_setup(int nr, struct
> >> > pci_sys_data *sys)
> >> > 
> >> >     if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
> >> >     
> >> >             sys->io_offset = global_io_offset -
> >> >             pp->config.io_bus_addr;
> >> > 
> >> > -           pci_ioremap_io(sys->io_offset, pp->io.start);
> >> > +           pci_ioremap_io(sys->io_offset, pp->io_base);
> >> > 
> >> >             global_io_offset += SZ_64K;
> >> >             pci_add_resource_offset(&sys->resources, &pp->io,
> >> >             
> >> >                                     sys->io_offset);
> >> 
> >> Tim, can you test if this patch fixes your SKY2 IOspace problem please ?
> > 
> > Above mentioned patch is NOT the latest patch.
> > Pratyush Anand already submitted the next patch as below.
> > 
> > Tim,
> > Would you test the following patch on i.MX6 platform?
> > 
> > diff --git a/drivers/pci/host/pcie-designware.c
> > b/drivers/pci/host/pcie-designware.c index be6ce30..b83f5e8 100644
> > --- a/drivers/pci/host/pcie-designware.c
> > +++ b/drivers/pci/host/pcie-designware.c
> > @@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> > 
> >                                            + global_io_offset);
> >                         
> >                         pp->config.io_size = resource_size(&pp->io);
> >                         pp->config.io_bus_addr = range.pci_addr;
> > 
> > +                       pp->io_base = range.cpu_addr;
> > 
> >                 }
> >                 if (restype == IORESOURCE_MEM) {
> >                 
> >                         of_pci_range_to_resource(&range, np, &pp->mem);
> > 
> > @@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> > 
> >         pp->cfg0_base = pp->cfg.start;
> >         pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
> > 
> > -       pp->io_base = pp->io.start;
> > 
> >         pp->mem_base = pp->mem.start;
> >         
> >         pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
> > 
> > @@ -667,7 +667,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data
> > *sys)
> > 
> >         if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
> >         
> >                 sys->io_offset = global_io_offset -
> >                 pp->config.io_bus_addr;
> > 
> > -               pci_ioremap_io(sys->io_offset, pp->io.start);
> > +               pci_ioremap_io(global_io_offset, pp->io_base);
> > 
> >                 global_io_offset += SZ_64K;
> >                 pci_add_resource_offset(&sys->resources, &pp->io,
> >                 
> >                                         sys->io_offset);
> > 
> > Best regards,
> > Jingoo Han
> 
> Yes, this patch resolves the issue and now I can use devices with io
> resources behind a bridge attached to the IMX6.
> 
> Thanks everyone for your efforts!

This is awesome, thanks guys!
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Jingoo Han Dec. 10, 2013, 11:58 p.m. UTC | #3 
On Wednesday, December 11, 2013 8:24 AM, Tim Harvey wrote:
> On Tue, Dec 10, 2013 at 2:22 PM, Jingoo Han <jg1.han@samsung.com> wrote:
> > On Tuesday, December 10, 2013 10:27 PM, Marek Vasut wrote:
> >> On Monday, December 09, 2013 at 08:12:42 AM, Pratyush Anand wrote:
> >
> > [.....]
> >
> >> >
> >> > diff --git a/drivers/pci/host/pcie-designware.c
> >> > b/drivers/pci/host/pcie-designware.c index be6ce30..cf68632 100644
> >> > --- a/drivers/pci/host/pcie-designware.c
> >> > +++ b/drivers/pci/host/pcie-designware.c
> >> > @@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >> >                                        + global_io_offset);
> >> >                     pp->config.io_size = resource_size(&pp->io);
> >> >                     pp->config.io_bus_addr = range.pci_addr;
> >> > +                   pp->io_base = range.cpu_addr;
> >> >             }
> >> >             if (restype == IORESOURCE_MEM) {
> >> >                     of_pci_range_to_resource(&range, np, &pp->mem);
> >> > @@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >> >
> >> >     pp->cfg0_base = pp->cfg.start;
> >> >     pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
> >> > -   pp->io_base = pp->io.start;
> >> >     pp->mem_base = pp->mem.start;
> >> >
> >> >     pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
> >> > @@ -667,7 +667,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data
> >> > *sys)
> >> >
> >> >     if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
> >> >             sys->io_offset = global_io_offset - pp->config.io_bus_addr;
> >> > -           pci_ioremap_io(sys->io_offset, pp->io.start);
> >> > +           pci_ioremap_io(sys->io_offset, pp->io_base);
> >> >             global_io_offset += SZ_64K;
> >> >             pci_add_resource_offset(&sys->resources, &pp->io,
> >> >                                     sys->io_offset);
> >>
> >> Tim, can you test if this patch fixes your SKY2 IOspace problem please ?
> >
> > Above mentioned patch is NOT the latest patch.
> > Pratyush Anand already submitted the next patch as below.
> >
> > Tim,
> > Would you test the following patch on i.MX6 platform?
> >
> > diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> > index be6ce30..b83f5e8 100644
> > --- a/drivers/pci/host/pcie-designware.c
> > +++ b/drivers/pci/host/pcie-designware.c
> > @@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >                                            + global_io_offset);
> >                         pp->config.io_size = resource_size(&pp->io);
> >                         pp->config.io_bus_addr = range.pci_addr;
> > +                       pp->io_base = range.cpu_addr;
> >                 }
> >                 if (restype == IORESOURCE_MEM) {
> >                         of_pci_range_to_resource(&range, np, &pp->mem);
> > @@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >
> >         pp->cfg0_base = pp->cfg.start;
> >         pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
> > -       pp->io_base = pp->io.start;
> >         pp->mem_base = pp->mem.start;
> >
> >         pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
> > @@ -667,7 +667,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
> >
> >         if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
> >                 sys->io_offset = global_io_offset - pp->config.io_bus_addr;
> > -               pci_ioremap_io(sys->io_offset, pp->io.start);
> > +               pci_ioremap_io(global_io_offset, pp->io_base);
> >                 global_io_offset += SZ_64K;
> >                 pci_add_resource_offset(&sys->resources, &pp->io,
> >                                         sys->io_offset);
> >
> >
> > Best regards,
> > Jingoo Han
> >
> 
> Yes, this patch resolves the issue and now I can use devices with io
> resources behind a bridge attached to the IMX6.
> 
> Thanks everyone for your efforts!

Wow, happy ending! :-)
I was deeply moved.

Pratyush Anand,
Would you re-send this patch with commit message?
You did a good job! I really appreciate your patch.

Best regards,
Jingoo Han

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diff mbox

Patch

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index be6ce30..b83f5e8 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -378,6 +378,7 @@  int __init dw_pcie_host_init(struct pcie_port *pp)
 					   + global_io_offset);
 			pp->config.io_size = resource_size(&pp->io);
 			pp->config.io_bus_addr = range.pci_addr;
+			pp->io_base = range.cpu_addr;
 		}
 		if (restype == IORESOURCE_MEM) {
 			of_pci_range_to_resource(&range, np, &pp->mem);
@@ -403,7 +404,6 @@  int __init dw_pcie_host_init(struct pcie_port *pp)
 
 	pp->cfg0_base = pp->cfg.start;
 	pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
-	pp->io_base = pp->io.start;
 	pp->mem_base = pp->mem.start;
 
 	pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
@@ -667,7 +667,7 @@  static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
 
 	if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
 		sys->io_offset = global_io_offset - pp->config.io_bus_addr;
-		pci_ioremap_io(sys->io_offset, pp->io.start);
+		pci_ioremap_io(global_io_offset, pp->io_base);
 		global_io_offset += SZ_64K;
 		pci_add_resource_offset(&sys->resources, &pp->io,
 					sys->io_offset);