Message ID | 1392742567-6134-1-git-send-email-greearb@candelatech.com (mailing list archive) |
---|---|
State | Not Applicable, archived |
Headers | show |
greearb@candelatech.com writes: > From: Ben Greear <greearb@candelatech.com> > > This appears to fix the problem of running out of keys > in the firmware. Possibly it only hides the problem, > however. > > Signed-off-by: Ben Greear <greearb@candelatech.com> IIRC you asked me to drop this patch in other thread. I have now done that.
On 02/26/2014 08:48 AM, Kalle Valo wrote: > greearb@candelatech.com writes: > >> From: Ben Greear <greearb@candelatech.com> >> >> This appears to fix the problem of running out of keys >> in the firmware. Possibly it only hides the problem, >> however. >> >> Signed-off-by: Ben Greear <greearb@candelatech.com> > > IIRC you asked me to drop this patch in other thread. I have now done > that. Yes, it breaks upstream firmware (looks like it asserts, but not sure exactly why). I still think it might be a problem, but it would take someone with newer firmware source and/or better understanding of how the keys are supposed to work to know for sure. Thanks, Ben
diff --git a/drivers/net/wireless/ath/ath10k/hw.h b/drivers/net/wireless/ath/ath10k/hw.h index 89167d5..dede8e0 100644 --- a/drivers/net/wireless/ath/ath10k/hw.h +++ b/drivers/net/wireless/ath/ath10k/hw.h @@ -83,7 +83,7 @@ enum ath10k_mcast2ucast_mode { #define TARGET_NUM_PEERS 16 #define TARGET_NUM_OFFLOAD_PEERS 0 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 -#define TARGET_NUM_PEER_KEYS 2 +#define TARGET_NUM_PEER_KEYS (WMI_MAX_KEY_INDEX + 1) /* 4 */ #define TARGET_NUM_TIDS (2 * ((TARGET_NUM_PEERS) + (TARGET_NUM_VDEVS))) #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) @@ -125,7 +125,7 @@ enum ath10k_mcast2ucast_mode { #define TARGET_10X_NUM_OFFLOAD_PEERS 0 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 -#define TARGET_10X_NUM_PEER_KEYS 2 +#define TARGET_10X_NUM_PEER_KEYS (WMI_MAX_KEY_INDEX + 1) /* 4 */ #define TARGET_10X_NUM_TIDS 256 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))